Hello Heiko
  > Sorry for having to bring up the process again,
  but the patch
  > author should match the Signed-off-by line.

  Apologies for the inconsistency. I'll fix that in v5.

  > Also is the last name always "UPPER CASE" in your
   region?

  Yes it is standard practice in France to write family names in all
capitals to distinguish them from given names, especially when the
family name could be confused with a given name, not my case but I
comply.

  v5 sent separately.

  Best regards,
  Midgy BALON


Le ven. 20 mars 2026 à 09:48, Heiko Stuebner [off-list ref] a écrit :

Am Donnerstag, 19. März 2026, 15:51:20 Mitteleuropäische Normalzeit schrieb MidG971:

quoted

The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
This chip is currently modeled only as a fixed regulator
(vcc3v3_pi6c_03), with no clock output representation.

The PI6C20100 is a clock generator, not a power supply. Model it
properly as a gated-fixed-clock, following the pattern established
for the Rock 5 ITX and other boards with similar PCIe clock buffer
chips.

The regulator node is kept as-is since it controls the power supply
to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
references this regulator as its vdd-supply and provides a proper
100MHz clock output. The pcie3x2 node is updated to include the
pipe and reference clocks, matching the approach used in
rk3588-rock-5-itx.dts.

Assisted-by: Claude:claude-3-opus
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Midgy BALON <redacted>

Sorry for having to bring up the process again, but the patch
author should match the Signed-off-by line.

You can update the patch author with something like:
  git commit --author="Midgy BALON [off-list ref]" --amend

Also is the last name always "UPPER CASE" in your region?

Thanks a lot for staying on this
Heiko

quoted

---

Changes since v3 [1]:
 - Add Reviewed-by from Shawn Lin

Changes since v2 [2]:
 - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
 - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
   override (Shawn, referencing David's patch [3])

Changes since v1 [4]:
 - Drop phy-supply approach entirely (Jonas, Shawn)
 - Model PI6C20100 as gated-fixed-clock instead
 - Wire reference clock to pcie3x2 controller
 - Follow pattern from rk3588-rock-5-itx.dts

[1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/ (local)
[2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/ (local)
[3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1 (local)
[4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/ (local)

 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
index c5f67dd6dfd9..1a2b3c4d5e6f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts

@@ -56,7 +56,16 @@
              };
      };

-     /* pi6c pcie clock generator */
+     /* PI6C20100 PCIe reference clock buffer (100MHz) */
+     pcie30_refclk: pcie-clock-generator {
+             compatible = "gated-fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <100000000>;
+             clock-output-names = "pcie30_refclk";
+             vdd-supply = <&vcc3v3_pi6c_03>;
+     };
+
+     /* PI6C20100 power supply - active-high GPIO0_D4 */
      vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
              compatible = "regulator-fixed";
              enable-active-high;

@@ -553,6 +562,15 @@
 };

 &pcie3x2 {
+     clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+              <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+              <&cru CLK_PCIE30X2_AUX_NDFT>,
+              <&cru CLK_PCIE30X2_PIPE_DFT>,
+              <&pcie30_refclk>;
+     clock-names = "aclk_mst", "aclk_slv",
+                   "aclk_dbi", "pclk", "aux",
+                   "pipe", "ref";
      pinctrl-names = "default";
      pinctrl-0 = <&pcie30x2m1_pins>;
      reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
--

2.39.5