[PATCH v2 1/3] arm64: dts: freescale: imx95-toradex-smarc: Add SER2 interface
From: Franz Schnyder <hidden>
Date: 2026-03-26 14:37:35
Also in:
imx, linux-devicetree, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
From: Franz Schnyder <redacted> The Toradex SMARC iMX95 has four exposed serial interfaces, one of these is SER2, which supports RTS/CTS. Add UART support for SMARC SER2. Signed-off-by: Franz Schnyder <redacted> --- v2: no changes --- .../dts/freescale/imx95-toradex-smarc-dev.dts | 5 +++++ .../boot/dts/freescale/imx95-toradex-smarc.dtsi | 16 ++++++++++++++++ 2 files changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts
index 5b05f256fd52..7437e523ff63 100644
--- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts@@ -210,6 +210,11 @@ &lpuart3 { status = "okay"; }; +/* SMARC SER2 */ +&lpuart6 { + status = "okay"; +}; + /* SMARC MDIO, shared between all ethernet ports */ &netc_emdio { status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
index 7a73958f6eec..1d369983cf7d 100644
--- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi@@ -22,6 +22,7 @@ aliases { rtc1 = &scmi_bbm; serial0 = &lpuart2; serial1 = &lpuart1; + serial2 = &lpuart6; serial3 = &lpuart3; };
@@ -615,6 +616,13 @@ &lpuart3 { pinctrl-0 = <&pinctrl_uart3>; }; +/* SMARC SER2 */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; +}; + &mu7 { status = "okay"; };
@@ -1105,6 +1113,14 @@ pinctrl_uart3: uart3grp { <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>; /* SMARC P141 - SER3_RX */ }; + /* SMARC SER2 */ + pinctrl_uart6: uart6grp { + fsl,pins = <IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x31e>, /* SMARC P139 - SER2_CTS# */ + <IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e>, /* SMARC P138 - SER2_RTS# */ + <IMX95_PAD_GPIO_IO05__LPUART6_RX 0x31e>, /* SMARC P137 - SER2_RX */ + <IMX95_PAD_GPIO_IO04__LPUART6_TX 0x31e>; /* SMARC P136 - SER2_TX */ + }; + /* On-module eMMC */ pinctrl_usdhc1: usdhc1grp { fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */
--
2.43.0