[PATCH v7 5/5] arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support
From: Richard Zhu <hongxing.zhu@nxp.com>
Date: 2026-03-13 08:33:58
Also in:
imx, linux-devicetree, linux-pci, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
Add pcie[0,1] and pcie-ep[0,1] support. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- arch/arm64/boot/dts/freescale/Makefile | 4 + arch/arm64/boot/dts/freescale/imx943-evk.dts | 82 ++++++++++++++++++++ 2 files changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a6fe56bb93aa..e0d5148441c6 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile@@ -465,6 +465,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb +imx943-evk-pcie0-ep-dtbs += imx943-evk.dtb imx-pcie0-ep.dtbo +imx943-evk-pcie1-ep-dtbs += imx943-evk.dtb imx-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx943-evk-pcie0-ep.dtb imx943-evk-pcie1-ep.dtb + imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index c8ceabe3d923..f69c0b60b039 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts@@ -50,6 +50,20 @@ chosen { stdout-path = &lpuart1; }; + pcie_ref_clk: clock-pcie-ref { + compatible = "gpio-gate-clock"; + clocks = <&xtal25m>; + #clock-cells = <0>; + enable-gpios = <&pca9670_i2c3 7 GPIO_ACTIVE_LOW>; + }; + + xtal25m: clock-xtal25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "xtal_25MHz"; + }; + dmic: dmic { compatible = "dmic-codec"; #sound-dai-cells = <0>;
@@ -71,6 +85,15 @@ reg_m2_pwr: regulator-m2-pwr { startup-delay-us = <5000>; }; + reg_slot_pwr: regulator-slot-pwr { + compatible = "regulator-fixed"; + regulator-name = "PCIe slot-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6416_i2c3_u46 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_m2_wlan: regulator-wlan { compatible = "regulator-fixed"; regulator-name = "WLAN_EN";
@@ -653,6 +676,18 @@ IMX94_PAD_GPIO_IO28__LPI2C6_SCL 0x40000b9e >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B 0x4000031e + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + IMX94_PAD_GPIO_IO23__PCIE2_CLKREQ_B 0x4000031e + >; + }; + pinctrl_pdm: pdmgrp { fsl,pins = < IMX94_PAD_PDM_CLK__PDM_CLK 0x31e
@@ -821,6 +856,53 @@ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe }; }; +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>, + <&pcie_ref_clk>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", + "ref", "extref"; + reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>; + vpcie3v3aux-supply = <®_m2_wlan>; + supports-clkreq; + status = "okay"; +}; + +&pcie0_ep { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + vpcie-supply = <®_m2_wlan>; + status = "disabled"; +}; + +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>, + <&pcie_ref_clk>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", + "ref", "extref"; + reset-gpio = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>; + vpcie3v3aux-supply = <®_slot_pwr>; + status = "okay"; +}; + +&pcie1_ep { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + vpcie-supply = <®_slot_pwr>; + status = "disabled"; +}; + &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
--
2.37.1