在 2026/03/11 星期三 21:43, Anand Moon 写道:

Hi Shawn,

Thanks for your review comments.

On Wed, 11 Mar 2026 at 17:57, Shawn Lin [off-list ref] wrote:

quoted

在 2026/03/11 星期三 19:54, Anand Moon 写道:

quoted

Add supports-clkreq and the corresponding pinmux configurations for PCIe
ASPM L1 substates on the Rock 5B, 5B+, and 5T.
The supports-clkreq flag informs the PCIe controller that the hardware
routing for the CLKREQ# sideband signal is present. This enables support
for PCIe ASPM (Active State Power Management) L1 substates, allowing for
better power efficiency.

Cc: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Anand Moon <redacted>
---

I verified the change by comparing the lspci -vvv output from before
and after the modification.

quoted

It would be better if you could put the link to the schematic here(under
"---") for folks easy to review. I paste it here for reference：

https://dl.radxa.com/rock5/5b+/docs/hw/radxa_rock5bp_v1.2_schematic.pdf

Ok, I will follow this advice next time,

quoted

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   arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 9 ++++++---
   1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
index b3e76ad2d869..668b19c05f7e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi

@@ -468,7 +468,8 @@ map1 {

   &pcie2x1l0 {
       pinctrl-names = "default";
-     pinctrl-0 = <&pcie2_0_rst>;
+     pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>;
+     supports-clkreq;
       reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
       vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
       status = "okay";

@@ -476,7 +477,8 @@ &pcie2x1l0 {

   &pcie2x1l2 {
       pinctrl-names = "default";
-     pinctrl-0 = <&pcie2_2_rst>;
+     pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>;

Isn't it m1(PCIE20_1_2_CLKREQn_M1_L in the schematic)?

I just used the pinctrl label GPIO3_C7_u as a reference to select this
one. see below.

[1] https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi#L1613-L1662

The RK3588 Technical Reference Manual (TRM) Part 2 provides the
following details regarding the clkreq# signal
pcie_clkreq_in/out_n    M0 PCIE20X1_2_CLKREQN_M0 GPIO3_C7_u
pcie_clkreq_in/out_n    M1 PCIE20X1_2_CLKREQN_M1 GPIO4_B7_u

Okay, I checked it again, you are right. Apprently the schematic label
is insane which marks it as PCIE20_1_2_CLKREQn_M1_L....

quoted

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+     supports-clkreq;
       reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
       vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
       status = "okay";

@@ -488,7 +490,8 @@ &pcie30phy {

   &pcie3x4 {
       pinctrl-names = "default";
-     pinctrl-0 = <&pcie3_rst>;
+     pinctrl-0 = <&pcie3_rst>, <&pcie30x4m1_clkreqn>;

The pin is correct but I don't think it would support
L1 substates because the refclk is out of control. For
any refclk coming from external clock generator, clkreq#
should connect to the enable pin of the clock generator.

I did not find the external clkreq# signal for this #clkreq signal in
the schematics.

PCIE30X4_CLKREQn_M1_L  (GPIO4_B4_u) .

What I meant is PCIE30X4_CLKREQn_M1_L is connected between root port
and M.2 slot which is not the right hardware design to support L1 
substates with PCIe3.0 PHY. We could do that for combophy as the refclk
is auto controlled by controller when entering and exiting L1 substates.
But for PCIe3.0 PHY the refclk is always there coming from
Au5426_device, so the this port tries to enter L1 substates, no
component could turn off the refclk to meet the timing of entering L1
substate, except you connect clkreq# to the Au5426, because in that case
PHY could gate the incoming refclk via clkreq#, thanks to the natural
behaviour of how clkreq# is controlled.

To clarify, PCIE30X4_CLKREQn_M1_L is connected between the Root Port and
the M.2 slot. This hardware configuration is not suitable for supporting
L1 Substates with the PCIe 3.0 PHY. While this setup works for the Combo
PHY—where the controller automatically manages the reference clock
during L1 Substate entry and exit—it fails with the dedicated PCIe 3.0
PHY. In the latter case, the reference clock from the Au5426_device is
always active. Consequently, when this port attempts to enter L1
Substates, no component can gate the reference clock to meet the
required timing specifications.

The only way to satisfy the timing requirements is to connect CLKREQ# 
directly to the Au5426. This allows the PHY to gate the incoming 
reference clock via the CLKREQ# signal, leveraging its standard control 
behavior.

Otherwise you could only see it in L1 instead of L1 substates. By the
way, how do you verfy it could enter L1 substate? Do you use debugfs
like below ?
   cat /sys/kernel/debug/dwc_pcie_a40000000.pcie/ltssm_status

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+     supports-clkreq;
       reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
       vpcie3v3-supply = <&vcc3v3_pcie30>;
       status = "okay";

base-commit: b29fb8829bff243512bb8c8908fd39406f9fd4c3

Thanks
-Anand