Re: [PATCH v1 2/2] iommu/arm-smmu-v3: Recover ATC invalidate timeouts

On Fri, Mar 06, 2026 at 09:02:02AM -0400, Jason Gunthorpe wrote:

On Thu, Mar 05, 2026 at 09:06:17PM -0800, Nicolin Chen wrote:

quoted

On Thu, Mar 05, 2026 at 09:33:47PM -0400, Jason Gunthorpe wrote:

quoted

On Thu, Mar 05, 2026 at 05:29:22PM -0800, Nicolin Chen wrote:

quoted

But arm_smmu_cmdq_issue_cmdlist() doesn't know when to push another
CMD. In my case where ATC_INV irq occurs, the return value from the
arm_smmu_cmdq_poll_until_sync() in the Step 5 is 0, and prods/cons
are also matched. Actually, at this point that NOP ISR has already
finished.

Yes, you'd need a sneaky way to convay the error from the ISR to the
cmdlist code that didn't harm performance. Maybe we could come up with
something, but if it works replacing the NOP with flush sounds fairly
appealing - though can you do a single WORD edit to the STE that will
block translated requests? Zero EATS?

Yea. I can give that a try.

This also really needs to go after the invalidation changes because it
is feasible to also edit the lockless RCU invalidation list from the
ISR and disable the ATC for the failed device too.

Yea, it is likely something that we have to do to deduplicate new
ATC timeouts triggering another reset.

In general, the maximum users count of an INV_TYPE_ATS would be 1.
So, an unref() would be sufficient to mute it, though it'd require
the unref() API to support a mismatched users counter, because the
PCI reset in the WQ would block ATS, which would try to unref the
removed command once again.

Thanks
Nicolin