[PATCH v8 03/23] dt-bindings: ufs: mediatek,ufs: Add mt8196 variant
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Date: 2026-03-04 14:54:14
Also in:
linux-devicetree, linux-mediatek, linux-phy, linux-scsi, lkml
Subsystem:
open firmware and flattened device tree bindings, the rest, universal flash storage host controller driver · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
The MediaTek MT8196 SoC's UFS controller uses three additional clocks compared to the MT8195, and a different set of supplies. It is therefore not compatible with the MT8195. While it does have a AVDD09_UFS_1 pin in addition to the AVDD09_UFS pin, it appears that these two pins are commoned together, as the board schematic I have access to uses the same supply for both, and the downstream driver does not distinguish between the two supplies either. Add a compatible for it, and modify the binding correspondingly. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> --- .../devicetree/bindings/ufs/mediatek,ufs.yaml | 58 +++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
index e0aef3e5f56b..a82119ecbfe8 100644
--- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml@@ -16,10 +16,11 @@ properties: - mediatek,mt8183-ufshci - mediatek,mt8192-ufshci - mediatek,mt8195-ufshci + - mediatek,mt8196-ufshci clocks: minItems: 1 - maxItems: 13 + maxItems: 16 clock-names: minItems: 1
@@ -37,6 +38,9 @@ properties: - const: crypt_perf - const: ufs_rx_symbol0 - const: ufs_rx_symbol1 + - const: ufs_sel + - const: ufs_sel_min_src + - const: ufs_sel_max_src operating-points-v2: true
@@ -131,9 +135,27 @@ allOf: properties: clocks: minItems: 13 + maxItems: 13 clock-names: minItems: 13 + maxItems: 13 avdd09-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8196-ufshci + then: + properties: + clocks: + minItems: 16 + maxItems: 16 + clock-names: + minItems: 16 + maxItems: 16 + avdd18-supply: false + required: + - operating-points-v2 examples: - |
@@ -183,3 +205,37 @@ examples: mediatek,ufs-disable-mcq; }; + - | + #include <dt-bindings/reset/mediatek,mt8196-resets.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + ufshci@16810000 { + compatible = "mediatek,mt8196-ufshci"; + reg = <0x16810000 0x2a00>; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&ufs_ao_clk 6>, <&ufs_ao_clk 7>, <&clk26m>, <&ufs_ao_clk 3>, + <&clk26m>, <&ufs_ao_clk 4>, <&ufs_ao_clk 0>, + <&topckgen 7>, <&topckgen 41>, <&topckgen 105>, <&topckgen 83>, + <&ufs_ao_clk 1>, <&ufs_ao_clk 2>, <&topckgen 42>, + <&topckgen 84>, <&topckgen 102>; + clock-names = "ufs", "ufs_aes", "ufs_tick", "unipro_sysclk", + "unipro_tick", "unipro_mp_bclk", "ufs_tx_symbol", + "ufs_mem_sub", "crypt_mux", "crypt_lp", "crypt_perf", + "ufs_rx_symbol0", "ufs_rx_symbol1", "ufs_sel", + "ufs_sel_min_src", "ufs_sel_max_src"; + + operating-points-v2 = <&ufs_opp_table>; + + phys = <&ufsphy>; + + avdd09-supply = <&mt6363_vsram_modem>; + vcc-supply = <&mt6363_vemc>; + vccq-supply = <&mt6363_vufs12>; + + resets = <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_UNIPRO>, + <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_CRYPTO>, + <&ufs_ao_clk MT8196_UFSAO_RST1_UFSHCI>; + reset-names = "unipro", "crypto", "hci"; + mediatek,ufs-disable-mcq; + };
--
2.53.0