Re: [PATCH v3] PCI: dw-rockchip: Enable async probe by default
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: 2026-03-03 01:01:16
Also in:
linux-pci, linux-rockchip, lkml
在 2026/02/26 星期四 18:10, Anand Moon 写道:
Rockchip DWC PCIe driver currently performs synchronous link training for combo PHYs (PCIe 3.0/2.0 and SATA 3.0) during boot. This process waits for the link to be fully established, adding several milliseconds to the boot sequence. To optimize boot time, this change enables asynchronous probing, allowing link establishment to proceed in the background while the kernel continues probing other devices.
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
quoted hunk ↗ jump to hunk
Cc: Grimmauld <redacted> Cc: Niklas Cassel <cassel@kernel.org> Tested-by: Grimmauld <redacted> Signed-off-by: Anand Moon <redacted> --- v3: update the commit message to describe the changs. added tested by Grimmauld. https://lore.kernel.org/all/20240809073610.2517-1-linux.amoon@gmail.com/ (local) v2: update the commit message to describe the changs. --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 + 1 file changed, 1 insertion(+)diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 5b17da63151d5..c31e0e9848327 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c@@ -746,6 +746,7 @@ static struct platform_driver rockchip_pcie_driver = { .name = "rockchip-dw-pcie", .of_match_table = rockchip_pcie_of_match, .suppress_bind_attrs = true, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, }, .probe = rockchip_pcie_probe, };base-commit: f4d0ec0aa20d49f09dc01d82894ce80d72de0560