Re: [PATCH v25 1/4] dt-bindings: i2c: Split AST2600 binding into a new YAML
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: 2026-02-27 07:10:15
Also in:
linux-aspeed, linux-devicetree, linux-i2c, lkml, openbmc
On Wed, Feb 25, 2026 at 05:19:38PM +0800, Ryan Chen wrote:
The AST2600 I2C controller introduces a completely new register layout with separate controller and target register blocks, unlike the mixed register layout used by AST2400/AST2500. To describe this properly, split out the AST2600 I2C binding into its own YAML file. The compatible string remains unchanged.
But you made other changes in the binding. You must list them, because otherwise it sounds like you only SPLIT. It's not true. You actually changed the binding in at least two places, maybe more.
The example section is updated to reflect the actual AST2600 SoC
register layout and interrupt configuration (aspeed-g6.dtsi,
lines 885-897):
- I2C bus and buffer register offsets
- AST2600 I2C controller register base starts at 0x80, and the
buffer region is located at 0xc00, per the AST2600 SoC register map.
- Interrupt configuration
- AST2600 I2C controllers are connected to the ARM GIC, not the legacy
internal interrupt controller.Example is irrelevant, don't mention it. We discuss here binding.
quoted hunk ↗ jump to hunk
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> --- .../bindings/i2c/aspeed,ast2600-i2c.yaml | 62 ++++++++++++++++++++++ .../devicetree/bindings/i2c/aspeed,i2c.yaml | 3 +- 2 files changed, 63 insertions(+), 2 deletions(-)diff --git a/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml new file mode 100644 index 000000000000..077be85137c9 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml@@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/aspeed,ast2600-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED I2C on the AST26XX SoCs
s/26XX/2600/ probably
+
+maintainers:
+ - Ryan Chen [off-list ref]
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-i2c-bus
+
+ reg:
+ items:
+ - description: controller registers
+ - description: controller buffer space
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ description: Desired operating frequency of the I2C bus in Hz.
+ minimum: 500
+ maximum: 4000000
+ default: 100000
+
+ resets:
+ maxItems: 1
+
+required:
+ - reg
+ - compatible
+ - clocks
+ - resets
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/aspeed-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ i2c@80 {
+ #address-cells = <1>;
+ #size-cells = <0>;Please follow DTS coding style. Best regards, Krzysztof