Dragan Simic already had warned me of potential issues with 5.0 GT/s
speed operation in Rockchip PCIe. However, in recent interactions
with Shawn Lin from Rockchip it came to my attention there's grave
danger in the unknown errata regarding 5.0 GT/s operational speed
of their PCIe core.

Drop all code related to 5.0 GT/s operational speed from this driver.

Endpoint Mode driver was not tested. There's a bit of redundancy in the
commit messages but it's the best I could do to ensure people will
actually understand why perfectly working code is being dropped.

---

Changes in v4:
- Incorporate suggestion by Bjorn and refined by Dragan to drop the
  "catastrophic" code
- Link to v3: https://lore.kernel.org/linux-rockchip/cover.1772057799.git.geraldogabriel@gmail.com/T/ (local)

Changes in v3:
- Clarify warning message even though Rockchip won't disclose details
- Drop DT changes as they were applied as subset by Heiko
- Link to v2: https://lore.kernel.org/all/cover.1763415705.git.geraldogabriel@gmail.com/T/ (local)

Changes in v2:
- hard limit to 2.5 GT/s, not just warn
- add Reported-by: and Reviewed-by: Dragan Simic
- remove redundant declaration of max-link-speed from helios64 dts
- fix Link: of helios64 patch
- simplify RC mode comment
- Link to v1: https://lore.kernel.org/all/aRhR79u5BPtRRFw3@geday/T/ (local)


---

Geraldo Nascimento (4):
  PCI: rockchip: drop 2.5 GT/s defines
  PCI: rockchip: drive at 2.5 GT/s only and error out other speeds
  PCI: rockchip-host: do not attempt 5.0 GT/s retraining
  PCI: rockchip-ep: do not attempt 5.0 GT/s retraining

 drivers/pci/controller/pcie-rockchip-ep.c   | 13 -------------
 drivers/pci/controller/pcie-rockchip-host.c | 20 --------------------
 drivers/pci/controller/pcie-rockchip.c      | 13 +++++--------
 drivers/pci/controller/pcie-rockchip.h      |  3 ---
 4 files changed, 5 insertions(+), 44 deletions(-)

-- 
2.52.0