On Wed, Feb 25, 2026 at 2:20 PM CK Hu (胡俊光) [off-list ref] wrote:

On Tue, 2026-01-20 at 12:36 +0100, Gary Bisson wrote:

quoted

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Some bridges, such as the TI SN65DSI83, require the HS clock to be
running in order to lock its PLL during its own pre-enable function.

Without this change, the bridge gives the following error:
sn65dsi83 14-002c: failed to lock PLL, ret=-110
sn65dsi83 14-002c: Unexpected link status 0x01
sn65dsi83 14-002c: reset the pipe

Move the necessary functions from enable to pre-enable.

Looks good to me, but this change the flow for all SoC and panel,
so I would wait for more SoC and more panel test.

Reviewed-by: CK Hu <redacted>

Tested-by: Chen-Yu Tsai <wenst@chromium.org> # Chromebooks

Tested on:
- MT8173 Hana (Telesu) w/ PS8640 bridge
- MT8183 Krane w/ DSI panel
- MT8183 Juniper w/ ANX7625 bridge
- MT8186 Tentacruel w/ PS8640 bridge
- MT8186 Steelix w/ PS8640 bridge

No regressions observed.

quoted

Signed-off-by: Gary Bisson <redacted>
---
Tested on Tungsten510 module with sn65dsi83 + tm070jdhg30 panel.

Left mtk_dsi_set_mode() as part of the enable function to mimic what is
done in the Samsung DSIM driver which is known to be working the TI
bridge.
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 0e2bcd5f67b7..b560245d1be9 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c

@@ -672,6 +672,21 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
        }
 }

+static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
+{
+       if (!dsi->lanes_ready) {
+               dsi->lanes_ready = true;
+               mtk_dsi_rxtx_control(dsi);
+               usleep_range(30, 100);
+               mtk_dsi_reset_dphy(dsi);
+               mtk_dsi_clk_ulp_mode_leave(dsi);
+               mtk_dsi_lane0_ulp_mode_leave(dsi);
+               mtk_dsi_clk_hs_mode(dsi, 0);
+               usleep_range(1000, 3000);
+               /* The reaction time after pulling up the mipi signal for dsi_rx */
+       }
+}
+
 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 {
        struct device *dev = dsi->host.dev;

@@ -724,6 +739,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
        mtk_dsi_set_vm_cmd(dsi);
        mtk_dsi_config_vdo_timing(dsi);
        mtk_dsi_set_interrupt_enable(dsi);
+       mtk_dsi_lane_ready(dsi);
+       mtk_dsi_clk_hs_mode(dsi, 1);

        return 0;
 err_disable_engine_clk:

@@ -769,30 +786,12 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
        dsi->lanes_ready = false;
 }

-static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
-{
-       if (!dsi->lanes_ready) {
-               dsi->lanes_ready = true;
-               mtk_dsi_rxtx_control(dsi);
-               usleep_range(30, 100);
-               mtk_dsi_reset_dphy(dsi);
-               mtk_dsi_clk_ulp_mode_leave(dsi);
-               mtk_dsi_lane0_ulp_mode_leave(dsi);
-               mtk_dsi_clk_hs_mode(dsi, 0);
-               usleep_range(1000, 3000);
-               /* The reaction time after pulling up the mipi signal for dsi_rx */
-       }
-}
-
 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 {
        if (dsi->enabled)
                return;

-       mtk_dsi_lane_ready(dsi);
        mtk_dsi_set_mode(dsi);
-       mtk_dsi_clk_hs_mode(dsi, 1);
-
        mtk_dsi_start(dsi);

        dsi->enabled = true;

---
base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
change-id: 20260120-mtkdsi-29e4c84e7b38

Best regards,
--
Gary Bisson [off-list ref]

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