[PATCH v3 4/6] arm64: dts: mediatek: mt8167: Add DRM nodes
From: Luca Leonardo Scorcia <hidden>
Date: 2026-02-23 16:26:44
Also in:
dri-devel, linux-devicetree, linux-mediatek, linux-phy, lkml
Subsystem:
arm/mediatek soc support, the rest · Maintainers:
Matthias Brugger, AngeloGioacchino Del Regno, Linus Torvalds
Add all the DRM nodes required to get DSI to work on MT8167 SoC. Signed-off-by: Luca Leonardo Scorcia <redacted> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 317 +++++++++++++++++++++++ 1 file changed, 317 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 27cf32d7ae35..32d3895baaa6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi@@ -16,6 +16,20 @@ / { compatible = "mediatek,mt8167"; + aliases { + aal0 = &aal; + ccorr0 = &ccorr; + color0 = &color; + dither0 = &dither; + dsi0 = &dsi; + gamma0 = γ + ovl0 = &ovl0; + pwm0 = &disp_pwm; + rdma0 = &rdma0; + rdma1 = &rdma1; + wdma0 = &wdma; + }; + soc { topckgen: topckgen@10000000 { compatible = "mediatek,mt8167-topckgen", "syscon";
@@ -120,10 +134,303 @@ iommu: m4u@10203000 { #iommu-cells = <1>; }; + disp_pwm: pwm@1100f000 { + compatible = "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm"; + reg = <0 0x1100f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_PWM_26M>, <&mmsys CLK_MM_DISP_PWM_MM>; + clock-names = "main", "mm"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + status = "disabled"; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; #clock-cells = <1>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + + mmsys_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_in>; + }; + }; + }; + + ovl0: ovl0@14007000 { + compatible = "mediatek,mt8167-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { + remote-endpoint = <&mmsys_main>; + }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&color_in>; + }; + }; + }; + }; + + rdma0: rdma0@14009000 { + compatible = "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg = <0 0x14009000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&dither_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + }; + + rdma1: rdma1@1400a000 { + compatible = "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg = <0 0x1400a000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma1_in: endpoint { + remote-endpoint = <&mmsys_ext>; + }; + }; + + port@1 { + reg = <1>; + rdma1_out: endpoint { }; + }; + }; + }; + + wdma: wdma0@1400b000 { + compatible = "mediatek,mt8167-disp-wdma", "mediatek,mt8173-disp-wdma"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_WDMA0>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + color: color@1400c000 { + compatible = "mediatek,mt8167-disp-color"; + reg = <0 0x1400c000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + color_out: endpoint { + remote-endpoint = <&ccorr_in>; + }; + }; + }; + }; + + ccorr: ccorr@1400d000 { + compatible = "mediatek,mt8167-disp-ccorr", "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_CCORR>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr_in: endpoint { + remote-endpoint = <&color_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr_out: endpoint { + remote-endpoint = <&aal_in>; + }; + }; + }; + }; + + aal: aal@1400e000 { + compatible = "mediatek,mt8167-disp-aal", "mediatek,mt8173-disp-aal"; + reg = <0 0x1400e000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_AAL>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal_in: endpoint { + remote-endpoint = <&ccorr_out>; + }; + }; + + port@1 { + reg = <1>; + aal_out: endpoint { + remote-endpoint = <&gamma_in>; + }; + }; + }; + }; + + gamma: gamma@1400f000 { + compatible = "mediatek,mt8167-disp-gamma", "mediatek,mt8173-disp-gamma"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma_in: endpoint { + remote-endpoint = <&aal_out>; + }; + }; + + port@1 { + reg = <1>; + gamma_out: endpoint { + remote-endpoint = <&dither_in>; + }; + }; + }; + }; + + dither: dither@14010000 { + compatible = "mediatek,mt8167-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_DITHER>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither_in: endpoint { + remote-endpoint = <&gamma_out>; + }; + }; + + port@1 { + reg = <1>; + dither_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; + }; + + dsi: dsi@14012000 { + compatible = "mediatek,mt8167-dsi"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIGITAL>, + <&mipi_tx>; + clock-names = "engine", "digital", "hs"; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>; + phys = <&mipi_tx>; + phy-names = "dphy"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { }; + }; + }; + }; + + mutex: mutex@14015000 { + compatible = "mediatek,mt8167-disp-mutex"; + reg = <0 0x14015000 0 0x1000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; larb0: larb@14016000 {
@@ -145,6 +452,16 @@ smi_common: smi@14017000 { power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; + mipi_tx: dsi-phy@14018000 { + compatible = "mediatek,mt8167-mipi-tx", "mediatek,mt2701-mipi-tx"; + reg = <0 0x14018000 0 0x90>; + clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt8167-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>;
--
2.43.0