[PATCH v3 2/4] drm: atmel-hlcdc: configure LVDS PLL clock rate for LVDS Displays
From: Manikandan Muralidharan <manikandan.m@microchip.com>
Date: 2026-02-23 10:20:31
Also in:
dri-devel, lkml
Subsystem:
drm drivers, drm drivers and misc gpu patches, drm drivers for atmel hlcdc, the rest · Maintainers:
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Manikandan Muralidharan, Dharma Balasubiramani, Linus Torvalds
From: Dharma Balasubiramani <dharma.b@microchip.com> As per datasheet, The LVDS PLL clock runs at 7 times the panel pixel clock. Set the LVDS PLL clock to eliminate the need of assiging them in the DT and fallback to sys_clk for non-LVDS displays with proper error handling. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> --- Changes in v3: - Rephrase commit message and comment block Changes in v2: - Rephrase commit message and comment block --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 36 ++++++++++++++++--- 1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index b075f291847f..26c9fbdfd871 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c@@ -100,7 +100,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) drm_connector_list_iter_end(&iter); } - ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + else + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); if (ret) return;
@@ -187,7 +190,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK), cfg); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk); + else + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); } static enum drm_mode_status
@@ -243,7 +249,11 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, 10, 1000)) drm_warn(dev, "Atmel LCDC status register CLKSTS timeout\n"); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk); + else + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + pinctrl_pm_select_sleep_state(dev->dev); pm_runtime_allow(dev->dev);
@@ -256,15 +266,33 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, { struct drm_device *dev = c->dev; struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + struct drm_display_mode *adj = &c->state->adjusted_mode; struct regmap *regmap = crtc->dc->hlcdc->regmap; unsigned int status; + int ret; pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); pinctrl_pm_select_default_state(dev->dev); - clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + + /* + * Set LVDS PLL clock rate (7x pixel clock) if available + */ + if (crtc->dc->hlcdc->lvds_pll_clk) { + ret = clk_set_rate(crtc->dc->hlcdc->lvds_pll_clk, + (adj->clock * 7000)); + if (ret) { + drm_err(dev, "Failed to set LVDS PLL clk rate: %d\n", ret); + return; + } + ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + } else { + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + } + if (ret) + return; regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK); if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
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2.25.1