On Tue, Feb 17, 2026 at 11:57 PM Andre Przywara [off-list ref] wrote:

On Tue, 17 Feb 2026 17:30:03 +0800
Chen-Yu Tsai [off-list ref] wrote:

Hi,

quoted

When the PRCM clk driver was added, somehow the r-spi module clock
was skipped over.

Add it so that r-spi can actually work.

The patch itself looks fine, compared against the manual, so for that:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

But I noticed one thing below....

quoted

Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
---
 drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
index 0339c4af0fe5..db0e36d8838e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c

@@ -83,9 +83,22 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl",
 static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
                       &r_apb0_clk.common.hw, 0x13c, BIT(0), 0);

-/* SPI clock is /M/N (same as new MMC?) */

Ooops, looks like I saw that clock, but someone managed to dodge it :-(
Sorry about that.

quoted

+static const struct clk_parent_data r_spi_parents[] = {
+     { .fw_name = "hosc" },
+     { .fw_name = "pll-periph" },
+     { .name = "pll-periph0-300M" },
+     { .name = "pll-periph1-300M" },
+     { .name = "pll-audio" },

Looking a bit closer, all the PRCM PLL-AUDIO clocks in the manual refer to
AUDIO1PLL4X, which is provided by the MCU CCU, not AUDIO0PLL4X provided by

That's weird though, given that pll-audio1 only has /2 and /5 outputs.

The BSP code from https://github.com/radxa/allwinner-bsp.git also shows
pll-audio0-4x as the parent for the r_spi module clock. It does show
pll-audio1-4x as the parent for the ahbs clock, but "pll-audio1-4x" is
nowhere to be found.

So I think it's an error. Moreover, I think we might have discussed this
on IRC at the time?

the main CCU. So we would need to change the DT? I wonder if that breaks
boots with kernels which didn't know the MCU CCU yet (v6.15-v6.17)?

Did you mean new DT with old kernel? I think we don't really support that?

But even if you did do that, AFAIK the clk parent resolution is done
opportunistically, so if this one is missing, it would be fine as long
as no user is directly trying to select it with clk_set_parent(); and
even if they did, it would probably fail?

I could be wrong though.


Anyway, thanks for being thorough.


ChenYu

Cheers,
Andre.

quoted

+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150,
+                               0, 5,         /* M */
+                               8, 5,         /* P */
+                               24, 3,        /* mux */
+                               BIT(31),      /* gate */
+                               0);
 static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi",
                       &r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
+
 static SUNXI_CCU_GATE_HW(bus_r_spinlock_clk, "bus-r-spinlock",
                       &r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
 static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox",

@@ -138,6 +151,7 @@ static struct ccu_common *sun55i_a523_r_ccu_clks[] = {
      &bus_r_twd_clk.common,
      &r_pwmctrl_clk.common,
      &bus_r_pwmctrl_clk.common,
+     &r_spi_clk.common,
      &bus_r_spi_clk.common,
      &bus_r_spinlock_clk.common,
      &bus_r_msgbox_clk.common,

@@ -169,6 +183,7 @@ static struct clk_hw_onecell_data sun55i_a523_r_hw_clks = {
              [CLK_BUS_R_TWD]         = &bus_r_twd_clk.common.hw,
              [CLK_R_PWMCTRL]         = &r_pwmctrl_clk.common.hw,
              [CLK_BUS_R_PWMCTRL]     = &bus_r_pwmctrl_clk.common.hw,
+             [CLK_R_SPI]             = &r_spi_clk.common.hw,
              [CLK_BUS_R_SPI]         = &bus_r_spi_clk.common.hw,
              [CLK_BUS_R_SPINLOCK]    = &bus_r_spinlock_clk.common.hw,
              [CLK_BUS_R_MSGBOX]      = &bus_r_msgbox_clk.common.hw,