On Tue, Feb 17, 2026 at 10:54:49AM +0100, Marco Felsch wrote:

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Hi Ian,

On 26-02-17, Ian Ray wrote:

quoted

The PLL1443x is used to implement VIDEO_PLL1 on i.MX8MP and can be used
for dual-channel LVDS displays.  Add new rate 756 MHz, which divides by
7 to provide 108 MHz LVDS pixel clock, and by 2 for 378 MHz LDB clock.

the on-demand rate calculation doe for the PLL1443X PLLs is not
sufficient for you?

Apologies! The on-demand rate calculation does indeed work. So please
ignore this patch.

(The patch was needed on kernel 6.12 IIRC, and I automatically re-based
it on 6.18 without re-testing. Once again, apologies for the noise.)

Regards,
  Marco

quoted

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
---
 drivers/clk/imx/clk-pll14xx.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index 36d0e80b55b8..84279cf9f12b 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c

@@ -63,6 +63,7 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {

 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
      PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
+     PLL_1443X_RATE(756000000U, 252, 2, 2, 0),
      PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
      PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
      PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
--

2.49.0

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