[PATCH v1 2/3] arm64: dts: imx943: add pcie1 and pcie1-ep supports
From: Richard Zhu <hongxing.zhu@nxp.com>
Date: 2026-02-06 05:49:16
Also in:
imx, linux-devicetree, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
Add pcie1 and pcie1-ep supports. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- arch/arm64/boot/dts/freescale/imx943.dtsi | 76 +++++++++++++++++++++++ 1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
index 45b8da758e877..0df9d24cf985d 100644
--- a/arch/arm64/boot/dts/freescale/imx943.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx943.dtsi@@ -145,4 +145,80 @@ l3_cache: l3-cache { cache-unified; }; }; + + soc { + pcie1: pcie@4c380000 { + compatible = "fsl,imx95-pcie"; + reg = <0 0x4c380000 0 0x10000>, + <8 0x80100000 0 0xfe00000>, + <0 0x4c3e0000 0 0x10000>, + <0 0x4c3c0000 0 0x4000>; + reg-names = "dbi", "config", "atu", "app"; + ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, + <0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <3>; + msi-map = <0x0 &its 0x98 0x1>, + <0x100 &its 0x99 0x7>; + msi-map-mask = <0x1ff>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + num-viewport = <8>; + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "pme", "intr"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; + assigned-clocks =<&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + fsl,max-link-speed = <3>; + status = "disabled"; + }; + + pcie1_ep: pcie-ep@4c380000 { + compatible = "fsl,imx95-pcie-ep"; + reg = <0 0x4c380000 0 0x10000>, + <0 0x4c3e0000 0 0x1000>, + <0 0x4c3a0000 0 0x1000>, + <0 0x4c3c0000 0 0x4000>, + <0 0x4c3f0000 0 0x10000>, + <0xa 0 1 0>; + reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + assigned-clocks =<&scmi_clk IMX94_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX94_CLK_HSIOPLL>, + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>; + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; + assigned-clock-parents = <0>, <0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + msi-map = <0x0 &its 0x98 0x1>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + status = "disabled"; + }; + }; };
--
2.37.1