[PATCH V2 0/2] arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

This patch set adds usdhc1 support to enable M.2 SDIO WiFi on the
i.MX8MP EVK. The M.2 connector on this board can operate in both PCIe
and SDIO modes, and SDIO-based WLAN modules require proper power control
through the same M.2 WLAN enable line (W_DISABLE1 on pin 56).

Patch 1 corrects the IOMUX configuration by enabling the pull-select bit
for the M.2 regulator GPIO, ensuring that the weak pull-up is actually
applied.
Patch 2 enables usdhc1 and associated pinctrl settings needed for SDIO
WiFi operation on the M.2 connector.

---
Changes in V2:
1. Add fixes tag for patch#1.
2. Remove the patch which renames the regulator node from reg_pcie0 to
   reg_m2_wlan, instead add second label reg_m2_wlan to simply code.
---

Sherry Sun (2):
  arm64: dts: imx8mp-evk: Enable pull select bit for PCIe regulator GPIO
    (M.2 W_DISABLE1)
  arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 63 +++++++++++++++++++-
 1 file changed, 61 insertions(+), 2 deletions(-)

-- 
2.37.1

The current pin configuration for MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06
sets the weak pull-up but does not enable the pull select field.
Bit 8 in the IOMUX register must be set in order for the weak pull-up
to actually take effect.

Update the pinctrl setting from 0x40 to 0x140 to enable both the pull
select and the weak pull-up, ensuring the line behaves as expected.

Fixes: d50650500064 ("arm64: dts: imx8mp-evk: Add PCIe support")
Signed-off-by: Sherry Sun <redacted>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 3f9b3fab8ac3..a1269c7a6cc2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts

@@ -1069,7 +1069,7 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40
 
 	pinctrl_pcie0_reg: pcie0reggrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
 		>;
 	};
 

-- 
2.37.1

Add usdhc1 to support M.2 SDIO WiFi on i.MX8MP EVK board.

Signed-off-by: Sherry Sun <redacted>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 61 +++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index a1269c7a6cc2..dfcdcc739ec6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts

@@ -134,7 +134,7 @@ reg_audio_pwr: regulator-audio-pwr {
 		enable-active-high;
 	};
 
-	reg_pcie0: regulator-pcie {
+	reg_m2_wlan: reg_pcie0: regulator-pcie {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pcie0_reg>;

@@ -250,6 +250,13 @@ cpu {
 		};
 	};
 
+	usdhc1_pwrseq: usdhc1_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc1_pwrseq>;
+		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+	};
+
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;

@@ -863,6 +870,19 @@ &uart3 {
 	status = "okay";
 };
 
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	keep-power-in-suspend;
+	non-removable;
+	wakeup-source;
+	mmc-pwrseq = <&usdhc1_pwrseq>;
+	vmmc-supply = <&reg_m2_wlan>;
+	status = "okay";
+};
+
 &usdhc2 {
 	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 	assigned-clock-rates = <400000000>;

@@ -1169,6 +1189,45 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
 		>;
 	};
 
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
+		>;
+	};
+
+	pinctrl_usdhc1_pwrseq: usdhc1pwrseq {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10	0x140
+		>;
+	};
+
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190

-- 
2.37.1

On Thu, Feb 05, 2026 at 03:34:53PM +0800, Sherry Sun wrote:

The current pin configuration for MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06
sets the weak pull-up but does not enable the pull select field.
Bit 8 in the IOMUX register must be set in order for the weak pull-up
to actually take effect.

Update the pinctrl setting from 0x40 to 0x140 to enable both the pull
select and the weak pull-up, ensuring the line behaves as expected.

Fixes: d50650500064 ("arm64: dts: imx8mp-evk: Add PCIe support")
Signed-off-by: Sherry Sun <redacted>
---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

On Thu, Feb 05, 2026 at 03:34:54PM +0800, Sherry Sun wrote:

Add usdhc1 to support M.2 SDIO WiFi on i.MX8MP EVK board.

Signed-off-by: Sherry Sun <redacted>
---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

On Thu, 05 Feb 2026 15:34:52 +0800, Sherry Sun wrote:

This patch set adds usdhc1 support to enable M.2 SDIO WiFi on the
i.MX8MP EVK. The M.2 connector on this board can operate in both PCIe
and SDIO modes, and SDIO-based WLAN modules require proper power control
through the same M.2 WLAN enable line (W_DISABLE1 on pin 56).

Patch 1 corrects the IOMUX configuration by enabling the pull-select bit
for the M.2 regulator GPIO, ensuring that the weak pull-up is actually
applied.
Patch 2 enables usdhc1 and associated pinctrl settings needed for SDIO
WiFi operation on the M.2 connector.

[...]

Applied, thanks!

[1/2] arm64: dts: imx8mp-evk: Enable pull select bit for PCIe regulator GPIO (M.2 W_DISABLE1)
      (no commit info)
[2/2] arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support
      (no commit info)

Best regards,
--
Frank Li [off-list ref]

On Thu, Feb 05, 2026 at 03:34:54PM +0800, Sherry Sun wrote:

Add usdhc1 to support M.2 SDIO WiFi on i.MX8MP EVK board.

Signed-off-by: Sherry Sun <redacted>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 61 +++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

...

+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
+		>;
+	};
+
+	pinctrl_usdhc1_pwrseq: usdhc1pwrseq {

replace usdhc1pwrseq with usdhc1pwrseqgrp. Please run CHECK_DTBS before
post patch next time.

Frank

+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10	0x140
+		>;
+	};
+
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
--
2.37.1