Re: [PATCH] RISC-V: Skip stopping cycle counter
From: Anup Patel <anup@brainfault.org>
Date: 2026-02-04 10:45:44
Also in:
linux-perf-users, linux-riscv, lkml
On Mon, Feb 2, 2026 at 4:48 PM qingwei.hu [off-list ref] wrote:
quoted hunk ↗ jump to hunk
From: Qingwei Hu <redacted> In the riscv_pmu_sbi driver, pmu_sbi_stop_all() is intended to stop all available counters. However, counter 0 (the cycle counter) should be excluded from this operation because the counter may be used in user mode by rdcycle. Signed-off-by: Qingwei Hu <redacted> --- drivers/perf/riscv_pmu_sbi.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 7dd282da67ce..2bc0050dabd2 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c@@ -900,11 +900,15 @@ static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) { /* - * No need to check the error because we are disabling all the counters - * which may include counters that are not enabled yet. + * No need to check the error because we are disabling all available + * counters (except the cycle counter) which may include counters + * that are not enabled yet. + * + * Cycle counter is excluded because it might be accessed by user + * mode via rdcycle. */ sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, - 0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); + 0, pmu->cmask & ~BIT(0), SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
NAK to this patch. Disabling all counters (including cycle and instret counters) is intentional. Please refer to past discussions. Regards, Anup
} static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) -- 2.39.5