RE: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets
From: "Pandey, Radhey Shyam" <radhey.shyam.pandey@amd.com>
Date: 2026-02-04 08:32:06
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linux-devicetree, linux-pci, linux-phy, lkml
[AMD Official Use Only - AMD Internal Distribution Only]
-----Original Message----- From: Sean Anderson <sean.anderson@linux.dev> Sent: Tuesday, February 3, 2026 5:51 AM To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>; Vinod Koul [off-list ref]; linux-phy@lists.infradead.org Cc: Krzysztof Wilczyński <kwilczynski@kernel.org>; Lorenzo Pieralisi [off-list ref]; Pandey, Radhey Shyam [off-list ref]; linux-kernel@vger.kernel.org; Simek, Michal [off-list ref]; linux-arm-kernel@lists.infradead.org; linux- pci@vger.kernel.org; Neil Armstrong [off-list ref]; Rob Herring [off-list ref]; Havalige, Thippeswamy [off-list ref]; Manivannan Sadhasivam [off-list ref]; Bjorn Helgaas [off-list ref]; Sean Anderson [off-list ref]; Conor Dooley [off-list ref]; Krzysztof Kozlowski [off-list ref]; devicetree@vger.kernel.org Subject: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets Add resets so we can hold the bridge in reset while we perform phy calibration.
Seems like this should a required property? Rest looks fine to me.
quoted hunk ↗ jump to hunk
Signed-off-by: Sean Anderson <sean.anderson@linux.dev> --- .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yamlb/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 9de3c09efb6e..7efb3dd9955f 100644--- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml@@ -69,6 +69,18 @@ properties: power-domains: maxItems: 1 + resets: + maxItems: 3 + + reset-names: + items: + - description: APB register block reset + const: cfg + - description: AXI-PCIe bridge reset + const: bridge + - description: PCIe MAC reset + const: ctrl + iommus: maxItems: 1@@ -117,6 +129,7 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> + #include <dt-bindings/reset/xlnx-zynqmp-resets.h> soc { #address-cells = <2>; #size-cells = <2>;@@ -146,6 +159,10 @@ examples: msi-parent = <&nwl_pcie>; phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; power-domains = <&zynqmp_firmware PD_PCIE>; + resets = <&zynqmp_reset ZYNQMP_RESET_PCIE_CFG>, + <&zynqmp_reset ZYNQMP_RESET_PCIE_BRIDGE>, + <&zynqmp_reset ZYNQMP_RESET_PCIE_CTRL>; + reset-names = "cfg", "bridge", "ctrl"; iommus = <&smmu 0x4d0>; pcie_intc: legacy-interrupt-controller { interrupt-controller; --2.35.1.1320.gc452695387.dirty