[PATCH RFC v2 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts
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STALE267d
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From: Jan Petrous via B4 Relay <devnull+jan.petrous.oss.nxp.com@kernel.org>
Date: 2026-01-21 14:23:56
Also in:
b4-sent, imx, linux-devicetree, lkml, netdev
Subsystem:
arm/nxp s32g/s32r dwmac ethernet driver, networking drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
Jan Petrous, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Revision v2 of 12 in this series.
Revisions (12)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines, set them to allow using Multi-IRQ mode when supported. Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> --- .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 42 +++++++++++++++++++--- 1 file changed, 37 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
index 2b8b74c5feec..e1ebc3bea095 100644
--- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml@@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2021-2024 NXP +# Copyright 2021-2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
@@ -33,10 +33,22 @@ properties: - description: GMAC PHY mode control register interrupts: - maxItems: 1 + minItems: 1 + maxItems: 11 interrupt-names: - const: macirq + - items: + - const: macirq + - const: rx-queue-0 + - const: tx-queue-0 + - const: rx-queue-1 + - const: tx-queue-1 + - const: rx-queue-2 + - const: tx-queue-2 + - const: rx-queue-3 + - const: tx-queue-3 + - const: rx-queue-4 + - const: tx-queue-4 clocks: items:
@@ -75,8 +87,28 @@ examples: reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent = <&gic>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 0: tx, rx */ + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 1: tx, rx */ + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 2: tx, rx */ + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 3: tx, rx */ + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 4: tx, rx */ + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
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2.47.0