Hi Hans,

On Wed, 7 Jan 2026 at 16:22, Hans de Goede [off-list ref] wrote:

Hi,

On 7-Jan-26 10:52, 张永波 wrote:

quoted

quoted

Still ideally we would solve this in another way then
switching to a threaded IRQ handler.

As the commit message of the mei-vsc fix mentions
the root cause of these errors is typically an interrupt
chip driver which uses IRQF_NO_THREAD disabling the auto
threading of all interrupt handlers in RT mode.

So the first question here would be to see if that flag is
used in the interrupt chip and if yes, is that flag really
necessary ?

This is very similar to the issue addressed in commit 24b176d8827d
("drm/msm/dsi: Remove spurious IRQF_ONESHOT flag").
The IRQF_ONESHOT flag is preventing forced threading here.

In irq_setup_forced_threading(), the conversion to threaded interrupts
is explicitly skipped if any of the IRQF_NO_THREAD, IRQF_PERCPU,
or IRQF_ONESHOT flags are present. In this case, IRQF_ONESHOT
appears to be the reason.

Ah, well the code effectively does its own IRQF_ONESHOT handling,
since it needs to do its own threaded-irq like handling for
suspend/resume reasons. It disables the IRQ when it fires and
then only re-enables it once the work has done processing the IRQ.

So it should be perfectly safe to drop the IRQF_ONESHOT flag.

Yes, the warning disappears

If that also works to resolve the lockdep issue that would be
the preferred way of fixing this IMHO.

After applying these changes, the device initially triggered a hard reset;
And the board reboots. I need to find another way to fix this warning.

However, after several reboots, it returned to a normal boot sequence.

[   40.404525][ T5974] rockchip-dw-pcie a41000000.pcie: LTSSM_STATUS: 0x130011
[   40.404936][ T4957] r8169 0004:41:00.0: enabling Mem-Wr-Inval
[   40.406591][   T56] dwmmc_rockchip fe2d0000.mmc: IDMAC supports
32-bit address mode.
[   40.407370][   T56] dwmmc_rockchip fe2d0000.mmc: Using internal DMA
controller.
[   40.408013][   T56] dwmmc_rockchip fe2d0000.mmc: Version ID is 270a
[   40.408610][   T56] dwmmc_rockchip fe2d0000.mmc: DW MMC controller
at irq 104,32 bit host data width,256 deep fifo
[   40.413373][   T56] mmc_host mmc2: card is non-removable.
[   40.431072][   T56] mmc_host mmc2: Bus speed (slot 0) = 400000Hz
(slot req 400000Hz, actual 400000HZ div = 0)
[   40.468235][   T67] mmc_host mmc2: Bus speed (slot 0) = 300000Hz
(slot req 300000Hz, actual 300000HZ div = 0)
[   40.492229][ T4957] r8169 0004:41:00.0 eth0: RTL8125B,
00:e0:4c:68:00:35, XID 641, IRQ 153
[   40.492993][ T4957] r8169 0004:41:00.0 eth0: jumbo features
[frames: 16362 bytes, tx checksumming: ko]
[   40.493873][ T4957] r8169 0004:41:00.0: vgaarb: pci_notify
[   40.507133][ T5974] rockchip-dw-pcie a41000000.pcie: Received Link
up event. Starting enumeration!
[   40.508219][ T5974] pci_bus 0004:40: scanning bus
[   40.517387][ T5974] pcieport 0004:40:00.0: scanning [bus 41-41]
behind bridge, pass 0
[   40.517867][   T67] mmc_host mmc2: Bus speed (slot 0) = 200000Hz
(slot req 200000Hz, actual 200000HZ div = 0)
[   40.518336][ T5974] pci_bus 0004:41: scanning bus
[   40.519531][ T5974] pci_bus 0004:41: bus scan returning with max=41
[   40.520294][ T5974] pcieport 0004:40:00.0: scanning [bus 41-41]
behind bridge, pass 1
[   40.521273][ T5974] pci_bus 0004:40: bus scan returning with max=41
DDR ff1a08bde6 typ 25/03/13-15:39:39,fwver: v1.19
ch0 ttot10
ch1 ttot10
ch2 ttot10
ch3 ttot10
ch0 ttot16
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
ch1 ttot16
channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
ch2 ttot16
channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
ch3 ttot16
channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
Manufacturer ID:0x6

Regards,

Hans

Thanks
-Anand