Re: [PATCH v1 0/3] clk: meson: small fixes for HDMI PLL OD

Hi Jerome,

On Tue, Jan 6, 2026 at 11:25 AM Jerome Brunet [off-list ref] wrote:
[...]

quoted

Martin Blumenstingl (3):
  clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
  clk: meson: g12a: Limit the HDMI PLL OD to /4
  clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro

Looks good.

I'd like to add a comment like this in the code

+/*
+ * GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.
+ * A divider value of 3 should map to /8 but instead map /4 so ignore it.
+ */

(and a similar one for the G12). Is this Ok with you ?

Sure, I'm happy to either have you add the comment when applying or me
doing it and sending a v2 - whichever you prefer.

Best regards,
Martin