On Mon, 24 Nov 2025 16:34:47 +0530, Pritam Manohar Sutar wrote:

This SoC has a single USB 3.1 DRD combo phy and three USB2.0 only
DRD phy controllers as mentined below

  * Combo phy supports USB3.1 SSP+(10Gbps) protocol and is backwards
    compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is added
    to support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates.
    These two phys are combined to form a combo phy as mentioned below.

[...]

Applied, thanks!

[1/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 HS phy compatible
      commit: 28810c0dfe8aa82e6514858bdcd7a83f0848e90a
[2/6] phy: exynos5-usbdrd: support HS phy for ExynosAutov920
      commit: 031314bd37cb6ce352b1300ffd4e07a7bebce1ef
[3/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo hsphy
      commit: fc58d4628396e4ae2791ff2396793d04940348e1
[4/6] phy: exynos5-usbdrd: support HS combo phy for ExynosAutov920
      commit: 22a401c9a2e1e27a136088e4291bec49869cecf5
[5/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo ssphy
      commit: 05681c9c7e59c164d7e1fc34696f3130d088bc64
[6/6] phy: exynos5-usbdrd: support SS combo phy for ExynosAutov920
      commit: 2fdfc1bb752e393561cf532f5d54607d70e464bc

Best regards,
-- 
~Vinod