Hi Jerome,
Thanks for coming back to review. Y

On 12/23/2025 4:59 PM, Jerome Brunet wrote:

[ EXTERNAL EMAIL ]

On Tue 28 Oct 2025 at 17:52, Chuan Liu via B4 Relay [off-list ref] wrote:

quoted

From: Chuan Liu <redacted>

Add the SCMI clock controller dt-bindings for the Amlogic A5 SoC
family.

Signed-off-by: Chuan Liu <redacted>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>

Please read:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.19-rc1#n503

and adjust your patches accordingly

Thanks for pointing that out. I'll address it.

quoted

---
  include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++++++++++++++++++++++++
  1 file changed, 44 insertions(+)

diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h
new file mode 100644
index 000000000000..1bf027d0110a
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef __AMLOGIC_A5_SCMI_CLKC_H
+#define __AMLOGIC_A5_SCMI_CLKC_H
+
+#define CLKID_OSC                            0
+#define CLKID_SYS_CLK                                1
+#define CLKID_AXI_CLK                                2
+#define CLKID_CPU_CLK                                3
+#define CLKID_DSU_CLK                                4
+#define CLKID_GP1_PLL                                5
+#define CLKID_FIXED_PLL_DCO                  6
+#define CLKID_FIXED_PLL                              7
+#define CLKID_ACLKM                          8
+#define CLKID_SYS_PLL_DIV16                  9
+#define CLKID_CPU_CLK_DIV16                  10
+#define CLKID_FCLK_50M_PREDIV                        11
+#define CLKID_FCLK_50M_DIV                   12
+#define CLKID_FCLK_50M                               13
+#define CLKID_FCLK_DIV2_DIV                  14
+#define CLKID_FCLK_DIV2                              15
+#define CLKID_FCLK_DIV2P5_DIV                        16
+#define CLKID_FCLK_DIV2P5                    17
+#define CLKID_FCLK_DIV3_DIV                  18
+#define CLKID_FCLK_DIV3                              19
+#define CLKID_FCLK_DIV4_DIV                  20
+#define CLKID_FCLK_DIV4                              21
+#define CLKID_FCLK_DIV5_DIV                  22
+#define CLKID_FCLK_DIV5                              23
+#define CLKID_FCLK_DIV7_DIV                  24
+#define CLKID_FCLK_DIV7                              25
+#define CLKID_SYS_MMC_PCLK                   26
+#define CLKID_SYS_CPU_CTRL                   27
+#define CLKID_SYS_IRQ_CTRL                   28
+#define CLKID_SYS_GIC                                29
+#define CLKID_SYS_BIG_NIC                    30
+#define CLKID_AXI_SYS_NIC                    31
+#define CLKID_AXI_CPU_DMC                    32
+
+#endif /* __AMLOGIC_A5_SCMI_CLKC_H */

--
Jerome