[PATCH 4/4] arm64: dts: rockchip: Add the vdpu346 Video Decoders on RK356X
From: Christian Hewitt <hidden>
Date: 2025-12-06 08:28:28
Also in:
linux-devicetree, linux-media, linux-rockchip, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
Add the vdpu346 Video Decoders to the rk356x-base devicetree to enable support on RK3566 and RK3568 boards. Also add the needed sram and vdec_mmu nodes. Suggested-by: Diederik de Haas <redacted> Suggested-by: Piotr Oniszczuk <redacted> Signed-off-by: Christian Hewitt <redacted> --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index c005135089d4..c51179e13657 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi@@ -383,6 +383,19 @@ usb2phy1_grf: syscon@fdca8000 { reg = <0x0 0xfdca8000 0x0 0x8000>; }; + sram@fdcc0000 { + compatible = "mmio-sram"; + reg = <0x0 0xfdcc0000 0x0 0xb000>; + ranges = <0x0 0x0 0xfdcc0000 0xb000>; + #address-cells = <1>; + #size-cells = <1>; + + vdec_sram: rkvdec-sram@0 { + reg = <0x0 0xb000>; + pool; + }; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>;
@@ -619,6 +632,42 @@ vepu_mmu: iommu@fdee0800 { #iommu-cells = <0>; }; + vdec: video-codec@fdf80100 { + compatible = "rockchip,rk3568-vdec"; + reg = <0x0 0xfdf80200 0x0 0x500>, + <0x0 0xfdf80100 0x0 0x100>, + <0x0 0xfdf80700 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC>, + <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_CA>, + <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <297000000>, <297000000>, + <297000000>, <600000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3568_PD_RKVDEC>; + resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, + <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&vdec_sram>; + }; + + vdec_mmu: iommu@fdf80800 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3568_PD_RKVDEC>; + #iommu-cells = <0>; + }; + sdmmc2: mmc@fe000000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe000000 0x0 0x4000>;
--
2.34.1