Re: [PATCH V2 3/3] arm64: dts: nvidia: Add nodes for CMDQV

On 12/1/2025 7:41 PM, Thierry Reding wrote:

On Mon, Dec 01, 2025 at 03:06:55PM +0530, Ashish Mhetre wrote:

quoted

On 11/25/2025 3:52 PM, Jon Hunter wrote:

quoted

On 25/11/2025 07:16, Ashish Mhetre wrote:

quoted

The Command Queue Virtualization (CMDQV) hardware is part of the
SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
virtualizing the command queue for the SMMU.

Update SMMU compatible strings to use nvidia,tegra264-smmu to enable
CMDQV support. Add device tree nodes for the CMDQV hardware and enable
them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU
instance is paired with its corresponding CMDQV instance via the
nvidia,cmdqv property.

Signed-off-by: Ashish Mhetre <redacted>
---
   .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi |  8 +++
   arch/arm64/boot/dts/nvidia/tegra264.dtsi      | 55 +++++++++++++++++--
   2 files changed, 58 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi

b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
index 06795c82427a..375d122b92fa 100644

--- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi

@@ -26,5 +26,13 @@ iommu@5000000 {
           iommu@6000000 {
               status = "okay";
           };
+
+        cmdqv@5200000 {
+            status = "okay";
+        };

This needs to be ordered in the file according to its address.

Hi Jon, Thanks for the review.
cmdqv nodes follow same ordering as its corresponding iommu nodes.
I have added them immediately after corresponding iommu nodes.

No, you didn't. It seems like you sorted by type and then address. But
we always sort by address first. Type doesn't matter.

This node belongs above the iommu@6000000 node and after iommu@5000000.
The same ordering should be respected in the DTS include.

Thierry

Oh, I got it. Thanks for clarification. I'll make these changes in v3.