Re: [PATCH v2 1/2] dt-bindings: memory-controllers: mtk-smi: Add support for mt8189
From: Zhengnan Chen (陈征南) <hidden>
Date: 2025-11-01 08:49:53
Also in:
linux-devicetree, linux-mediatek, lkml
On Thu, 2025-10-30 at 11:43 -0500, Rob Herring wrote:
External email : Please do not click links or open attachments until you have verified the sender or the content. On Mon, Oct 27, 2025 at 08:14:27PM +0800, Zhengnan Chen wrote:quoted
Add binding description for mt8189. The clocks number of mt8189 smi-sub common has a bit difference. Its clock count is 2, while mt8195 has 3. Therefore, the minimum number of clocks is changed to 2, with the third one being optional. About what smi-sub-common is, please check the below diagram, we add it in mediatek,smi-common.yaml file. Signed-off-by: Zhengnan Chen <redacted> --- Hi Angelo, We add a diagram in the smi-common yaml, We are not sure if you agree with this. thus I remove your R-b. Thanks. --- --- .../mediatek,smi-common.yaml | 25 +++++++++++++++++-- .../memory-controllers/mediatek,smi-larb.yaml | 3 +++ 2 files changed, 26 insertions(+), 2 deletions(-)diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory- controllers/mediatek,smi-common.yaml index 0762e0ff66ef..454d11a83973 100644--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml@@ -25,6 +25,21 @@ description: | SMI generation 1 to transform the smi clock into emi clockdomain, but that is not needed for SMI generation 2. + The smi-common connects with smi-larb and IOMMU. The maximum inputs number of + a smi-common is 8. In SMI generation 2, the engines number may be over 8. + In this case, we use a smi-sub-common to merge some larbs. + The block diagram something is like: + + IOMMU + | | + smi-common + --------------------------- + | | ... + larb0 sub-common ... <-max number is 8 + ---------------- + | | ... + larb1 larbX ... <-max number is 8 + properties: compatible: oneOf:@@ -40,6 +55,8 @@ properties: - mediatek,mt8186-smi-common - mediatek,mt8188-smi-common-vdo - mediatek,mt8188-smi-common-vpp + - mediatek,mt8189-smi-common + - mediatek,mt8189-smi-sub-common - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp@@ -108,19 +125,23 @@ allOf: compatible: contains: enum: + - mediatek,mt8189-smi-sub-common - mediatek,mt8195-smi-sub-common then: required: - mediatek,smi properties: clocks: - minItems: 3 + minItems: 2So now 2 clocks is valid for mt8195?
No, the mt8195 still requires 3 clock cycles. This approach can accommodate ICs that require 2 or 3 clocks simultaneously.
quoted
maxItems: 3 clock-names: + minItems: 2 + maxItems: 3 items: - const: apb - const: smi - - const: gals0 + additionalItems: + const: gals0 else: properties: mediatek,smi: falsediff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory- controllers/mediatek,smi-larb.yaml index 2e7fac4b5094..9a5dafd7c07e 100644--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml@@ -27,6 +27,7 @@ properties: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb@@ -85,6 +86,7 @@ allOf: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8195-smi-larb then:@@ -119,6 +121,7 @@ allOf: - mediatek,mt6779-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb --2.46.0