Hi, Krzysztof.

-----Original Message-----
From: Krzysztof Kozlowski <krzk@kernel.org>
Sent: Wednesday, October 22, 2025 5:31 PM
To: Nas Chung <nas.chung@chipsnmedia.com>; mchehab@kernel.org;
hverkuil@xs4all.nl; robh@kernel.org; krzk+dt@kernel.org;
conor+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de
Cc: linux-media@vger.kernel.org; devicetree@vger.kernel.org; linux-
kernel@vger.kernel.org; linux-imx@nxp.com; linux-arm-
kernel@lists.infradead.org; jackson.lee [off-list ref];
lafley.kim [off-list ref]; marek.vasut@mailbox.org
Subject: Re: [PATCH v4 2/9] dt-bindings: media: nxp: Add Wave6 video codec
device

On 22/10/2025 09:47, Nas Chung wrote:

quoted

Add documentation for the Chips&Media Wave6 video codec on
NXP i.MX SoCs.

The Wave6 video codec functionality is split between a VPU
control region and VPU core regions.
The VPU control region is represented as the parent node and
manages shared resources such as firmware memory. Each VPU
core region is represented as a child node and provides the
actual encoding and decoding capabilities.

Both the control and core regions may be assigned IOMMU
stream IDs for DMA isolation.

Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-
rc1/source/Documentation/process/submitting-patches.rst#L597

Thanks, I will address this in v5.

quoted

quoted

+
+  ranges: true
+
+patternProperties:
+  "^video-core@[0-9a-f]+$":
+    type: object
+    description:
+      A VPU core region within the Chips&Media Wave6 codec IP.
+      Each core provides encoding and decoding capabilities and operates
+      under the control of the VPU control region.

You explained more in previous email than in this description. Are these
independent? Can they be independently used?

No, they must be used together with the control region.
I will clarify this in v5.

But you also said there is one processing engine, so I do not understand
why these are separate. If you have one engine, there is no such thing
as separate cores.

Although the Wave6 VPU contains a single processing engine, it exposes up
to four hardware interfaces, each with its own MMIO region, interrupt
line, and IOMMU stream ID. These interfaces allow concurrent submission
of decoding/encoding operations via firmware scheduling, while execution
occurs on the single processing engine.

The control region also has its own MMIO region (global registers) and its
own IOMMU stream ID. Because the control and each interface have distinct
resources and stream IDs, I believe representing all regions as a single node
would be inappropriate.

Thanks.
Nas.

Best regards,
Krzysztof