Hi Elaine,

Am Mittwoch, 22. Oktober 2025, 05:21:43 Mitteleuropäische Sommerzeit schrieb zhangqing:

在 2025/10/21 16:38, Heiko Stuebner 写道:

quoted

Am Dienstag, 21. Oktober 2025, 08:52:27 Mitteleuropäische Sommerzeit schrieb Elaine Zhang:

quoted

Add clock and reset ID defines for rv1126b.
Also add documentation for the rv1126b CRU core.

Signed-off-by: Elaine Zhang <redacted>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
  .../bindings/clock/rockchip,rv1126b-cru.yaml  |  52 +++
  .../dt-bindings/clock/rockchip,rv1126b-cru.h  | 392 +++++++++++++++++
  .../dt-bindings/reset/rockchip,rv1126b-cru.h  | 405 ++++++++++++++++++
  3 files changed, 849 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
  create mode 100644 include/dt-bindings/clock/rockchip,rv1126b-cru.h
  create mode 100644 include/dt-bindings/reset/rockchip,rv1126b-cru.h

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
new file mode 100644
index 000000000000..04b0a5c51e4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1126b-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RV1126B Clock and Reset Unit
+
+maintainers:
+  - Elaine Zhang <zhangqing@rock-chips.com>
+  - Heiko Stuebner <heiko@sntech.de>
+
+description:
+  The rv1126b clock controller generates the clock and also implements a
+  reset controller for SoC peripherals.
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rv1126b-cru
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  "#reset-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: xin24m

I think we're missing the optional

    rockchip,grf:
      $ref: /schemas/types.yaml#/definitions/phandle
      description:
        Phandle to the syscon managing the "general register files" (GRF),
        if missing pll rates are not changeable, due to the missing pll
        lock status.


because RV1126B_GRF_SOC_STATUS0 contains the PLL lock status.

The pll lock truly uses bit10 of the PLL_CON1 register of CRU and does 
not use grf. Does that mean there is no need to increase rockchip,grf？

correct ... in that case we don't need the GRF reference.
As we're not accessing the GRF.

Please also drop the RV1126B_GRF_SOC_STATUS0 constant from the driver
in that case.

Thanks
Heiko