Thread (5 messages) 5 messages, 4 authors, 2025-11-20

Re: [PATCH] phy: exynos5-usbdrd: fix clock prepare imbalance

From: Peter Griffin <peter.griffin@linaro.org>
Date: 2025-10-07 20:18:49
Also in: linux-phy, linux-samsung-soc, lkml, stable

On Mon, 6 Oct 2025 at 09:07, André Draszik [off-list ref] wrote:
Commit f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend
with UDC bound (E850+)") incorrectly added clk_bulk_disable() as the
inverse of clk_bulk_prepare_enable() while it should have of course
used clk_bulk_disable_unprepare(). This means incorrect reference
counts to the CMU driver remain.

Update the code accordingly.

Fixes: f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)")
CC: stable@vger.kernel.org
Signed-off-by: André Draszik <andre.draszik@linaro.org>
---
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
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