On Sat, Sep 6, 2025 at 12:15 PM Chen-Yu Tsai [off-list ref] wrote:

On Wed, Sep 3, 2025 at 8:09 AM Andre Przywara [off-list ref] wrote:

quoted

A few of the Allwinner A523 CCU clock registers introduced an "update" bit,
which must be set for changes to the other bits to take effect.
Of the three clocks where this was used, it was always bit 27, so we just
encoded this as a single bit feature flag.

Now the CPU PLL also features the update bit, but puts it at bit 26, so
this flag trick won't work anymore.

Add an "update_bit" field to the common sunxi clock struct, which takes a
bitmask, so we can encode any bit to use, even potentially multiple of
them. As uninitialised fields are set to 0, we can use this as a default
bitmask to set, so can OR this in unconditionally.

Change the existing update bit users to use this new encoding, and add
support for the ccu_nm clock on the way, since we will need it there
shortly.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Chen-Yu Tsai <redacted>

Hmm, actually, we also have the "key field" feature. Maybe we should
generalize that one and merge the two?

What do you think?


ChenYu