[PATCH v5 3/3] arm64: dts: exynosautov920: Add multiple sensors
From: Shin Son <hidden>
Date: 2025-09-25 02:28:49
Also in:
linux-devicetree, linux-pm, linux-samsung-soc, lkml
Subsystem:
arm/samsung s3c, s5p and exynos arm architectures, the rest · Maintainers:
Krzysztof Kozlowski, Peter Griffin, Linus Torvalds
Create a new exynosautov920-tmu.dtsi describing new TMU hardware
and include it from exynosautov920.dtsi.
The exynosautov920-tmu node uses the misc clock as its source.
This TMU binding defines multiple thermal zones with a critical trip point
at 125 degrees:
tmu_top : cpus0-0, cpus0-1, cpus0-2, cpus0-3,
cpus1-0, cpus1-1, cpus1-2, cpus1-3,
cpus1-4, cpus1-5, cpus1-6, cpus1-7
tmu_sub0: cpus0-4, cpus0-5, cpus0-6, cpus0-7,
cpus2-0, cpus2-1, cpus2-2, cpus2-3
tmu_sub1: gpu0, gpu1, gpu2, gpu3, npu0, npu1
Signed-off-by: Shin Son <redacted>
---
.../boot/dts/exynos/exynosautov920-tmu.dtsi | 377 ++++++++++++++++++
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 31 ++
2 files changed, 408 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi
new file mode 100644
index 000000000000..641d142e0eeb
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi@@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's ExynosAuto920 TMU configurations device tree source + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * + * Samsung's ExynosAuto920 SoC TMU(Thermal Managemenut Unit) are listed as + * device tree nodes in this file. + */ + +/ { + thermal-zones { + cpus0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 9>; + + trips { + cpus0_0_critical: cpus0-0-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 10>; + + trips { + cpus0_1_critical: cpus0-1-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus0-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 11>; + + trips { + cpus0_2_critical: cpus0-2-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus0-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 12>; + + trips { + cpus0_3_critical: cpus0-3-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus0-4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub0 7>; + + trips { + cpus0_4_critical: cpus0-4-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus0-5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub0 8>; + + trips { + cpus0_5_critical: cpus0-5-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus0-6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub0 9>; + + trips { + cpus0_6_critical: cpus0-6-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus0-7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub0 10>; + + trips { + cpus0_7_critical: cpus0-7-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 1>; + + trips { + cpus1_0_critical: cpus1-0-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 2>; + + trips { + cpus1_1_critical: cpus1-1-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus1-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 3>; + + trips { + cpus1_2_critical: cpus1-2-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus1-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 4>; + + trips { + cpus1_3_critical: cpus1-3-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus1-4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 5>; + + trips { + cpus1_4_critical: cpus1-4-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus1-5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 6>; + + trips { + cpus1_5_critical: cpus1-5-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus1-6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 7>; + + trips { + cpus1_6_critical: cpus1-6-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus1-7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_top 8>; + + trips { + cpus1_7_critical: cpus1-7-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub0 3>; + + trips { + cpus2_0_critical: cpus2-0-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub0 4>; + + trips { + cpus2_1_critical: cpus2-1-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus2-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub0 5>; + + trips { + cpus2_2_critical: cpus2-2-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpus2-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub0 6>; + + trips { + cpus2_3_critical: cpus2-3-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub1 1>; + + trips { + gpu0_critical: gpu0-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub1 2>; + + trips { + gpu1_critical: gpu1-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + gpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub1 3>; + + trips { + gpu2_critical: gpu2-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + gpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub1 4>; + + trips { + gpu3_critical: gpu3-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + npu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub1 6>; + + trips { + npu0_critical: npu0-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + npu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu_sub1 7>; + + trips { + npu1_critical: npu1-critical { + temperature = <125000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; + }; +};
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 0fdf2062930a..fba403e48aed 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi@@ -330,6 +330,36 @@ watchdog_cl1: watchdog@10070000 { samsung,cluster-index = <1>; }; + tmu_top: tmu@100a0000 { + compatible = "samsung,exynosautov920-tmu"; + reg = <0x100A0000 0x1000>; + interrupts = <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <1>; + clocks = <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names = "tmu_apbif"; + samsung,sensors = <12>; + }; + + tmu_sub0: tmu@100b0000 { + compatible = "samsung,exynosautov920-tmu"; + reg = <0x100B0000 0x1000>; + interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <1>; + clocks = <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names = "tmu_apbif"; + samsung,sensors = <10>; + }; + + tmu_sub1: tmu@100c0000 { + compatible = "samsung,exynosautov920-tmu"; + reg = <0x100C0000 0x1000>; + interrupts = <GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH>; + #thermal-sensor-cells = <1>; + clocks = <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names = "tmu_apbif"; + samsung,sensors = <7>; + }; + gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;
@@ -1507,3 +1537,4 @@ timer { }; #include "exynosautov920-pinctrl.dtsi" +#include "exynosautov920-tmu.dtsi"
--
2.50.1