[PATCH v4 2/3] arm64: dts: exynos: gs101: add CPU clocks
From: Tudor Ambarus <tudor.ambarus@linaro.org>
Date: 2025-09-24 15:15:22
Also in:
linux-devicetree, linux-samsung-soc, lkml
Subsystem:
arm/samsung s3c, s5p and exynos arm architectures, google tensor soc support, the rest · Maintainers:
Krzysztof Kozlowski, Peter Griffin, Linus Torvalds
Add the GS101 CPU clocks exposed through the ACPM protocol. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index f88d45a368af7ef88e8cdc84b3a81a63a753832c..7326801c9ebf270496997839185594c3c1776577 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi@@ -7,6 +7,7 @@ */ #include <dt-bindings/clock/google,gs101.h> +#include <dt-bindings/clock/google,gs101-acpm.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/samsung,exynos-usi.h>
@@ -72,6 +73,7 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0000>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>;
@@ -82,6 +84,7 @@ cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0100>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>;
@@ -92,6 +95,7 @@ cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0200>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>;
@@ -102,6 +106,7 @@ cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0300>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>;
@@ -112,6 +117,7 @@ cpu4: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0400>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>;
@@ -122,6 +128,7 @@ cpu5: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0500>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>;
@@ -132,6 +139,7 @@ cpu6: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-x1"; reg = <0x0600>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>;
@@ -142,6 +150,7 @@ cpu7: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-x1"; reg = <0x0700>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>;
--
2.51.0.536.g15c5d4f767-goog