Re: [PATCH 3/7] arm64: dts: imx8mp-venice-gw702x: reduce RGMII CLK drive strength
From: Peng Fan <hidden>
Date: 2025-09-18 07:58:51
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Hi Tim, On Tue, Sep 16, 2025 at 08:32:12AM -0700, Tim Harvey wrote:
quoted hunk ↗ jump to hunk
The i.MX8M Plus EQOS RGMII tracelength is less than 1in and does not require a x6 drive strength. Reduce the CLK drive strength to x1 for better emissions. Signed-off-by: Tim Harvey <tharvey@gateworks.com> --- arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi index a1232a4f8485..dd9eeb3479fd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi@@ -462,7 +462,7 @@ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x0
You also changed FSEL from 2 to 0. So I would add this in commit that if this matches: Since TXC is not a high frequency clock, use slow slew rate for lower emissions and better signal quality Regards Peng
>; }; -- 2.25.1