RE: [PATCH v2 2/2] PCI: imx6: Add a method to handle CLKREQ# override active low
From: Hongxing Zhu <hongxing.zhu@nxp.com>
Date: 2025-09-18 03:04:42
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imx, linux-pci, lkml
-----Original Message----- From: Bjorn Helgaas <helgaas@kernel.org> Sent: 2025年9月18日 6:24 To: Hongxing Zhu <hongxing.zhu@nxp.com> Cc: Frank Li <frank.li@nxp.com>; jingoohan1@gmail.com; l.stach@pengutronix.de; lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org; robh@kernel.org; bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] PCI: imx6: Add a method to handle CLKREQ# override active low On Wed, Sep 17, 2025 at 05:37:51PM +0800, Richard Zhu wrote:quoted
The CLKREQ# is an open drain, active low signal that is driven low by the card to request reference clock. But the CLKREQ# maybe reserved on some old device, compliant with CEM r3.0 or before. Thus, this signal wouldn't be driven low by these old devices.Can you include a citation to a relevant section in the CEM spec? Maybe the point is that CLKREQ# is an optional signal added in PCIe CEM r4.0, sec 2? If that's accurate, we can add it when applying, no need to repost for that.
Hi Bjorn: Thanks for your comments. The Pin12 of connector is reserved refer to CEM spec r3.0 sec6.1 Connector Pinout. CLKREQ# is defined in CEM spec r4.0, but it's optional refer to CEM r4.0 sec2. And, the Pin12 of connector is defined as CLKREQ# refer to CEM spec r4.0 sec6.1 Connector Pinout. That's all. Should I repost for that? Best Regards Richard Zhu
quoted
Since the reference clock controlled by CLKREQ# may be required by i.MX PCIe host too. To make sure this clock is ready even when the CLKREQ# isn't driven low by the card(e.x old cards described above), force CLKREQ# override active low for i.MX PCIe host during initialization. The CLKREQ# override can be cleared safely when supports-clkreq is present and PCIe link is up later. Because the CLKREQ# would be driven low by the card in this case.