Re: [PATCH v6 1/5] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8ULP compatible string
From: Frank Li <Frank.li@nxp.com>
Date: 2025-09-17 15:54:05
Also in:
imx, linux-devicetree, linux-media, lkml
On Wed, Sep 17, 2025 at 04:14:50PM +0800, Guoniu Zhou wrote:
From: Guoniu Zhou <redacted> The CSI-2 receiver in the i.MX8ULP is almost identical to the version present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk clock as the input clock for its APB interface of Control and Status register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and increase maxItems of Clocks (clock-names) to 4 from 3. And keep the same restriction for existing compatible. Signed-off-by: Guoniu Zhou <redacted> ---
There are long discussion at previous verison. For refer: https://lore.kernel.org/imx/20250903192142.GA10637@pendragon.ideasonboard.com/ (local) compatible string "fsl,imx8qxp-mipi-csi2", has clock A, B, C compatible string "fsl,imx8ulp-mipi-csi2", has clock A, B, C, D clock B is special one, driver need know clk-freqeuncy. Other clocks just enable/disable. The program module is the same. It is not important about if fsl,imx8ulp-mipi-csi2 need fallback to fsl,imx8qxp-mipi-csi2 since driver has to been updated, only one line additional change. To keep simple and strangh forward, don't set fsl,imx8ulp-mipi-csi2 fallback to fsl,imx8qxp-mipi-csi2. Reviewed-by: Frank Li <Frank.Li@nxp.com>
quoted hunk ↗ jump to hunk
.../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 41 ++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-)diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml index 3389bab266a9adbda313c8ad795b998641df12f3..da3978da1cab75292ada3f24837443f7f4ab6418 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml@@ -20,6 +20,7 @@ properties: - enum: - fsl,imx8mq-mipi-csi2 - fsl,imx8qxp-mipi-csi2 + - fsl,imx8ulp-mipi-csi2 - items: - const: fsl,imx8qm-mipi-csi2 - const: fsl,imx8qxp-mipi-csi2@@ -39,12 +40,16 @@ properties: clock that the RX DPHY receives. - description: ui is the pixel clock (phy_ref up to 333Mhz). See the reference manual for details. + - description: pclk is clock for csr APB interface. + minItems: 3 clock-names: items: - const: core - const: esc - const: ui + - const: pclk + minItems: 3 power-domains: maxItems: 1@@ -130,19 +135,51 @@ allOf: compatible: contains: enum: - - fsl,imx8qxp-mipi-csi2 + - fsl,imx8ulp-mipi-csi2 + then: + properties: + reg: + minItems: 2 + resets: + minItems: 2 + maxItems: 2 + clocks: + minItems: 4 + clock-names: + minItems: 4 + + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-mipi-csi2 then: properties: reg: minItems: 2 resets: maxItems: 1 - else: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-mipi-csi2 + then: properties: reg: maxItems: 1 resets: minItems: 3 + clocks: + maxItems: 3 + clock-names: + maxItems: 3 required: - fsl,mipi-phy-gpr --2.34.1