[PATCH v1 3/5] clk: samsung: clk-pll: Add support for pll_1419x
From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Date: 2025-09-14 12:21:24
Also in:
linux-clk, linux-devicetree, linux-samsung-soc, lkml
Subsystem:
common clk framework, samsung soc clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Peter Griffin, Linus Torvalds
The PLL is similar to pll_35xx, with the following differences:
- different locktime - 150 instead of 270, as with pll_142xx
- different rate calculation
When defining a PLL, the "con" parameter should be set to CON0
register, like this:
PLL(pll_1419x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
pll_shared0_rate_table),
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
---
drivers/clk/samsung/clk-pll.c | 10 ++++++++--
drivers/clk/samsung/clk-pll.h | 10 ++++++++++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index acb366f14..6b3593445 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c@@ -229,7 +229,11 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; - fvco *= mdiv; + if (pll->type == pll_1419x) + fvco *= (2 * mdiv); + else + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); return (unsigned long)fvco;
@@ -273,7 +277,8 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, } /* Set PLL lock time. */ - if (pll->type == pll_142xx || pll->type == pll_141xx) + if (pll->type == pll_142xx || pll->type == pll_141xx || + pll->type == pll_1419x) writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, pll->lock_reg); else
@@ -1373,6 +1378,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_1450x: case pll_1451x: case pll_1452x: + case pll_1419x: case pll_141xx: case pll_142xx: pll->enable_offs = PLL35XX_ENABLE_SHIFT;
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 989addfdb..c07d76121 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h@@ -50,6 +50,7 @@ enum samsung_pll_type { pll_0732x, pll_4311, pll_141xx, + pll_1419x, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
@@ -57,6 +58,15 @@ enum samsung_pll_type { #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \ BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout))) +#define PLL_1419X_RATE(_fin, _rate, _m, _p, _s) \ + { \ + .rate = PLL_VALID_RATE(_fin, _rate, \ + 2 * _m, _p, _s, 0, 16), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + } + #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \ { \ .rate = PLL_VALID_RATE(_fin, _rate, \
--
2.43.0