Re: [v2 2/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl
From: Rob Herring <robh@kernel.org>
Date: 2025-09-12 14:19:17
Also in:
linux-devicetree, linux-gpio, lkml
On Fri, Sep 12, 2025 at 02:06:49PM +0800, Gary Yang wrote:
The pin-controller is used to control the Soc pins. There are two pin-controllers on Cix Sky1 platform. One is used under S0 state, the other is used under S5 state.
Wrap lines at 72 chars.
quoted hunk ↗ jump to hunk
Signed-off-by: Gary Yang <redacted> --- .../bindings/pinctrl/cix,sky1-pinctrl.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yamldiff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml new file mode 100644 index 000000000000..c4a127fd8330 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml@@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 Pin Controller + +maintainers: + - Gary Yang <gary.yang@cixtech.com> + +description: + The pin-controller is used to control Soc pins. There are two pin-controllers + on Cix Sky1 platform. one is used under S0 state, the other one is used under + S5 state. + +properties: + compatible: + enum: + - cix,sky1-iomuxc + - cix,sky1-iomuxc-s5 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +# Client device subnode's properties +patternProperties: + 'pins$': + type: object + additionalProperties: false + patternProperties: + '(^pins|pins?$)': + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, and drive strength. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h directly. + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + description: + Can support 15 levels, from DS_LEVEL1 to DS_LEVEL15. + See arch/arm64/boot/dts/cix/sky1-pinfunc.h for valid arguments.
Constraints on the values?
+
+ required:
+ - pinmux
+
+additionalProperties: false
+
+examples:
+ # Pinmux controller node
+ - |
+ #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0)
+ #define DS_LEVEL4 (4)
+ iomuxc: pinctrl@4170000 {
+ compatible = "cix,sky1-iomuxc";
+ reg = <0x4170000 0x1000>;
+
+ wifi_vbat_gpio: wifi-vbat-gpio-pins {
+ pins-wifi-vbat-gpio {
+ pinmux = <CIX_PAD_GPIO012_FUNC_GPIO012>;
+ bias-pull-up;
+ drive-strength = <DS_LEVEL4>;
+ };
+ };
+ };
--
2.49.0