Thread (18 messages) 18 messages, 5 authors, 2025-09-16

Re: [PATCH 1/4] dt-bindings: net: dsa: nxp,sja1105: Add reset-gpios property

flat view

From: Mark Brown <broonie@kernel.org>
Date: 2025-09-10 15:09:14
Also in: imx, linux-devicetree, linux-sound, lkml, netdev

On Wed, Sep 10, 2025 at 05:43:28PM +0300, Vladimir Oltean wrote:
On Wed, Sep 10, 2025 at 04:30:44PM +0200, Marco Felsch wrote:
quoted
Can you please elaborate a bit more? I was curious and checked the
AH1704, it says:
quoted
"The RST_N signal must be kept low for at least 5 us after all power
supplies and reference clock signals become stable."
quoted
This is very common, so the driver only needs to ensure that the pin was
pulled low for at least 5us but not exact 5us.
The statement says that during power-up, when the supply voltages and
clocks rise in order to become within spec, the reset signal must be
held low. This requirement lasts for up to 5 us more after the other
signals are in spec.
...
I said that _while the supplies and clocks aren't in spec and 5 us after
they become in spec_, RST_N has to be kept low.
And if you plan to do that from the GPIO function of your SoC, the SoC
might be busy doing other stuff, like booting, and no one might be
driving the RST_N voltage to a defined state.
I suspect you're reading too much into the datasheet there.  I suspect
that what it's trying to say is that the reset signal only works with
stable power and clocks, that it must be held low for the 5us while
those conditions hold and that you have to do at least one cold reset
after power on.  The above wording is pretty common in datasheets and I
know in a bunch of cases it was carried forward kind of blindly rather
than looking at the actual device requirements.
It really depends on a lot of factors including the reset timing and
supply voltage distribution of the PCB, but RST_N has essentially 2
purposes. One is ensuring proper POR sequencing, the other is cold
resetting at runtime. You can do the latter over SPI with identical
outcome, which leaves proper POR sequencing, which is not best served by
a GPIO in my experience.
I'm not sure not including the signal in the DT bindings is going to
influence board designers much either way TBH.

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