Re: [PATCH] clk: at91: clk-master: Add check for divide by 3
From: Nicolas Ferre <nicolas.ferre@microchip.com>
Date: 2025-09-09 07:57:36
Also in:
linux-clk, lkml
On 08/09/2025 at 22:07, Ryan.Wanner@microchip.com wrote:
From: Ryan Wanner <Ryan.Wanner@microchip.com> A potential divider for the master clock is div/3. The register configuration for div/3 is MASTER_PRES_MAX. The current bit shifting method does not work for this case. Checking for MASTER_PRES_MAX will ensure the correct decimal value is stored in the system. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Thanks Ryan, regards, Nicolas
quoted hunk ↗ jump to hunk
--- drivers/clk/at91/clk-master.c | 3 +++ 1 file changed, 3 insertions(+)diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 7a544e429d34..d5ea2069ec83 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c@@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw, { struct clk_master *master = to_clk_master(hw); + if (master->div == MASTER_PRES_MAX) + return DIV_ROUND_CLOSEST_ULL(parent_rate, 3); + return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); }