Le 29/08/2025 à 11:16, Krzysztof Kozlowski a écrit :

On 29/08/2025 10:35, Christophe Leroy wrote:

quoted

Le 29/08/2025 à 09:47, Krzysztof Kozlowski a écrit :

quoted

On 28/08/2025 16:12, Christophe Leroy wrote:

quoted

Le 28/08/2025 à 15:28, Rob Herring a écrit :

quoted

On Mon, Aug 25, 2025 at 2:20 AM Christophe Leroy
[off-list ref] wrote:

quoted

In the QE, a few GPIOs are IRQ capable. Similarly to
commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx
GPIO"), add IRQ support to QE GPIO.

Add property 'fsl,qe-gpio-irq-mask' similar to
'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs.

Why do you need to know this? The ones that have interrupts will be
referenced by an 'interrupts' property somewhere.

I don't follow you. The ones that have interrupts need to be reported by
gc->qe_gpio_to_irq[] so that gpiod_to_irq() return the IRQ number, for
instance to gpio_sysfs_request_irq() so that it can install an irq
handler. I can't see where they would be referenced by an "interrupts"
property.

They would be referenced by every consumer of these interrupts. IOW,
this property is completely redundant, because DT holds this information
already in other place.

But the gpio controller _is_ the consumer of these interrupts, it it
_not_ the provider.

The interrupts are provided by a separate interrupt controller. Let's
take the exemple of powerpc 8xx. Here is the list of interrupts handled
by the CPM interrupt controller on the 8xx:

1 - GPIO Port C Line 4 interrupt
2 - GPIO Port C Line 5 interrupt
3 - SMC2 Serial controller interrupt
4 - SMC1 Serial controller interrupt
5 - SPI controller interrupt
6 - GPIO Port C Line 6 interrupt
7 - Timer 4 interrupt
8 - SCCd Serial controller interrupt
9 - GPIO Port C Line 7 interrupt
10 - GPIO Port C Line 8 interrupt
11 - GPIO Port C Line 9 interrupt
12 - Timer 3 interrupt
13 - SCCc Serial controller interrupt
14 - GPIO Port C Line 10 interrupt
15 - GPIO Port C Line 11 interrupt
16 - I2C Controller interrupt
17 - RISC timer table interrupt
18 - Timer 2 interrupt
19 - SCCb Serial controller interrupt
20 - IDMA2 interrupt
21 - IDMA1 interrupt
22 - SDMA channel bus error interrupt
23 - GPIO Port C Line 12 interrupt
24 - GPIO Port C Line 13 interrupt
25 - Timer 1 interrupt
26 - GPIO Port C Line 14 interrupt
27 - SCCd Serial controller interrupt
28 - SCCc Serial controller interrupt
29 - SCCb Serial controller interrupt
30 - SCCa Serial controller interrupt
31 - GPIO Port C Line 15 interrupt

That list is fixed per soc/device, so already implied by compatible.

quoted

As you can see in the list, the GPIO line interrupts are nested with
other types of interrupts so GPIO controller and Interrupt controller
are to be keept independant.

That's more or less the same here with my series, patch 1 implements an
interrupt controller (documented in patch 6) and then the GPIO
controllers consume the interrupts, for instance in gpiolib functions
gpio_sysfs_request_irq() [drivers/gpio/gpiolib-sysfs.c] or
edge_detector_setup() or debounce_setup() [drivers/gpio/gpiolib-cdev.c]

External drivers also use interrupts indirectly. For example driver
sound/soc/soc-jack.c, it doesn't have any direct reference to an
interrupt. The driver is given an array of GPIOs and then installs an
IRQ in function snd_soc_jack_add_gpios() by doing

	request_any_context_irq(gpiod_to_irq(gpios[i].desc),
					      gpio_handler,
					      IRQF_SHARED |
					      IRQF_TRIGGER_RISING |
					      IRQF_TRIGGER_FALLING,
					      gpios[i].name,
					      &gpios[i]);

External drivers do not matter then. Your GPIO controller receives
specific interrupts (that's the interrupt property) and knows exactly
how each GPIO maps to it.

Do you mean then that the GPIO driver should already know which line has 
an interrupt and which one doesn't ?

The interrupts are fixed per soc, but today the GPIO driver is generic 
and used on different SOCs that don't have interrupts on the same lines. 
And even on the given SOCs, not all ports have interrupts on the same 
lines. Should all possibilities be hard-coded inside the driver for each 
possible compatible ? The property 'fsl,qe-gpio-irq-mask' is there to 
avoid that and keep the GPIO driver as generic as possible with a single 
compatible 'fsl,mpc8323-qe-pario-bank' that is found in the DTS of 8323 
but also in DTS of 8360, in DTS of 8569, etc... :

arch/powerpc/boot/dts/fsl/mpc8569mds.dts: 
             "fsl,mpc8323-qe-pario-bank";
arch/powerpc/boot/dts/fsl/mpc8569mds.dts: 
             "fsl,mpc8323-qe-pario-bank";
arch/powerpc/boot/dts/kmeter1.dts: 
     "fsl,mpc8323-qe-pario-bank";
arch/powerpc/boot/dts/mpc832x_rdb.dts: 
compatible = "fsl,mpc8323-qe-pario-bank";
arch/powerpc/boot/dts/mpc836x_rdk.dts: 
"fsl,mpc8323-qe-pario-bank";
arch/powerpc/boot/dts/mpc836x_rdk.dts: 
"fsl,mpc8323-qe-pario-bank";

Do you mean we should define one compatible for each of the ports of 
each soc, and encode the mask of interrupts that define which line of 
the port has interrupts in the data field ?

Something like:

static const struct of_device_id qe_gpio_match[] = {
	{
		.compatible = "fsl,mpc8323-qe-pario-bank-a",
		.data = (void *)0x00a00028,
	},
	{
		.compatible = "fsl,mpc8323-qe-pario-bank-b",
		.data = (void *)0x01400050,
	},
	{
		.compatible = "fsl,mpc8323-qe-pario-bank-c",
		.data = (void *)0x00000084,
	},
	{
		.compatible = "fsl,mpc8323-qe-pario-bank-d",
		.data = (void *)0,
	},
	{
		.compatible = "fsl,mpc8360-qe-pario-bank-a",
		.data = (void *)0xXXXXXXXX,
	},
	{
		.compatible = "fsl,mpc8360-qe-pario-bank-b",
		.data = (void *)0xXXXXXXXX,
	},
....
	{},
};
MODULE_DEVICE_TABLE(of, qe_gpio_match);

That would be feasible but would mean updating the driver each time a 
new SOC is added.

Do you mean it should be done that way ?

Isn't the purpose of the device tree to keep drivers as generic as 
possible ?

quoted

quoted

quoted

quoted

quoted

Here is an exemple for port B of mpc8323 which has IRQs for

typo

quoted

GPIOs PB7, PB9, PB25 and PB27.

           qe_pio_b: gpio-controller@1418 {
                   compatible = "fsl,mpc8323-qe-pario-bank";
                   reg = <0x1418 0x18>;
                   interrupts = <4 5 6 7>;
                   interrupt-parent = <&qepic>;
                   gpio-controller;
                   #gpio-cells = <2>;
                   fsl,qe-gpio-irq-mask = <0x01400050>;
           };

You are missing #interrupt-cells and interrupt-controller properties.

The gpio controller is not an interrupt controller. The GPIO controller
is brought by patch 1/6 and documented in patch 6/6.

Then the IRQ mask property is not right here. If you say "this GPIOs
have IRQs" it means this is an interrupt controller.

The mask tells to the GPIO controller which GPIO line has an interrupt
(so it can install the edge detector) and which doesn't have an
interrupt. The "interrupts" property gives a flat list of interrupts,
the mask in the above example tells: interrupt 4 is for line 7,
interrupt 5 is for line 9, interrupt 6 is for line 25, interrupt 7 is
for line 27. Other lines don't have interrupts.

quoted

If you say this is not an interrupt controller, then you cannot have
here interrupts per some GPIOs, obviously.

It has been working that way on powerpc 8xx for 8 years, since commit
726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx GPIO")

I don't understand why you say you cannot have
here interrupts per some GPIOs. What am I missing ?

I used conditional. English conditional. If you claim this GPIO
controller is not an interrupt controller, then obviously it is not an
interrupt controller and cannot be used as interrupt controller.

If you use "foo" as interrupt controller, then clearly foo is an
interrupt controller.

Ah ! ok. I didn't read it like that, sorry.

Thanks
Christophe