[PATCH 3/5] arm64: dts: amlogic: s6: add power domain controller node
From: Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@kernel.org>
Date: 2025-08-22 05:41:29
Also in:
b4-sent, linux-amlogic, linux-devicetree, linux-pm, lkml
Subsystem:
arm/amlogic meson soc support, the rest · Maintainers:
Neil Armstrong, Kevin Hilman, Linus Torvalds
From: "hongyu.chen1" <redacted> Add power domain controller node for Amlogic S6 SoC. Signed-off-by: hongyu.chen1 <redacted> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> --- arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
index 5f602f1170c0..0dca64a2ef9e 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi@@ -7,6 +7,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/amlogic,pinctrl.h> +#include <dt-bindings/power/amlogic,s6-pwrc.h> / { cpus { #address-cells = <2>;
@@ -41,6 +42,15 @@ cpu3: cpu@300 { }; }; + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + + pwrc: power-controller { + compatible = "amlogic,s6-pwrc"; + #power-domain-cells = <1>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--
2.37.1