[PATCH v2] clk: meson-g12a: fix bit range for fixed sys and hifi pll
From: Da Xue <hidden>
Date: 2025-08-22 00:22:08
Also in:
linux-amlogic, linux-clk, lkml
Subsystem:
arm/amlogic meson soc clock framework, common clk framework, the rest · Maintainers:
Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd, Linus Torvalds
The bit range 17:0 does not match the datasheet for A311D / S905D3.
Change the bit range to 18:0 for FIX and HIFI PLLs to match datasheet.
The frac field is missing for sys pll so add that as well.
Patched:
+ sudo cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq \
/sys/devices/system/cpu/cpufreq/policy2/cpuinfo_cur_freq
996999
500000
+ sudo cat /sys/kernel/debug/meson-clk-msr/measure_summary
+ grep -i '\(sys_\|hifi_\|fixed_\)pll'
hifi_pll 0 +/-1562Hz
sys_pll_div16 0 +/-1562Hz
sys_pll_cpub_div16 0 +/-1562Hz
+ sudo cat /sys/kernel/debug/clk/clk_summary
+ grep -i '\(sys_\|hifi_\|fixed_\)pll'
hifi_pll_dco 0 0 0 0
hifi_pll 0 0 0 0
sys_pll_dco 1 1 0 3999999985
sys_pll 0 0 0 499999999
sys_pll_div16_en 0 0 0 499999999
sys_pll_div16 0 0 0 31249999
fixed_pll_dco 1 1 1 3987999985
fixed_pll 3 3 1 1993999993
Unpatch:
+ sudo cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq \
/sys/devices/system/cpu/cpufreq/policy2/cpuinfo_cur_freq
1000000
500000
+ sudo cat /sys/kernel/debug/meson-clk-msr/measure_summary
+ grep -i '\(sys_\|hifi_\|fixed_\)pll'
hifi_pll 0 +/-1562Hz
sys_pll_div16 0 +/-1562Hz
sys_pll_cpub_div16 0 +/-1562Hz
+ sudo cat /sys/kernel/debug/clk/clk_summary
+ grep -i '\(sys_\|hifi_\|fixed_\)pll'
hifi_pll_dco 0 0 0 0
hifi_pll 0 0 0 0
sys_pll_dco 1 1 0 4800000000
sys_pll 0 0 0 1200000000
sys_pll_div16_en 0 0 0 1200000000
sys_pll_div16 0 0 0 75000000
fixed_pll_dco 1 1 1 3999999939
fixed_pll 3 3 1 1999999970
Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Da Xue <redacted>
---
drivers/clk/meson/g12a.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 66f0e817e416..f78cca619ca5 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c@@ -157,7 +157,7 @@ static struct clk_regmap g12a_fixed_pll_dco = { .frac = { .reg_off = HHI_FIX_PLL_CNTL1, .shift = 0, - .width = 17, + .width = 19, }, .l = { .reg_off = HHI_FIX_PLL_CNTL0,
@@ -223,6 +223,11 @@ static struct clk_regmap g12a_sys_pll_dco = { .shift = 10, .width = 5, }, + .frac = { + .reg_off = HHI_SYS_PLL_CNTL1, + .shift = 0, + .width = 19, + }, .l = { .reg_off = HHI_SYS_PLL_CNTL0, .shift = 31,
@@ -1901,7 +1906,7 @@ static struct clk_regmap g12a_hifi_pll_dco = { .frac = { .reg_off = HHI_HIFI_PLL_CNTL1, .shift = 0, - .width = 17, + .width = 19, }, .l = { .reg_off = HHI_HIFI_PLL_CNTL0,
--
2.47.2