Re: [PATCH 1/2] dt-bindings: timer: Add ARM SSE(Subsystems for Embedded) timer
From: Jisheng Zhang <jszhang@kernel.org>
Date: 2025-08-21 16:12:54
Also in:
linux-devicetree, linux-watchdog, lkml
On Thu, Aug 21, 2025 at 11:24:28PM +0800, Jisheng Zhang wrote:
quoted hunk
Add binding doc for the ARM SSE(Subsystems for Embedded) timer. Here is the document URL: https://developer.arm.com/documentation/107610/0000/System-timer-components?lang=en Although the IP is mostly seen on MCU SoC platforms, but nothing prevent it from being integrated into linux capable SoC platforms. The IP core may have a system counter to generate timestamp value, a system timer to raise an interrupt when a period has elapsed, and a System Watchdog to detect errant system behaviour then reset the system if a period elapses without ping. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- .../bindings/timer/arm,sse_timer.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/arm,sse_timer.yamldiff --git a/Documentation/devicetree/bindings/timer/arm,sse_timer.yaml b/Documentation/devicetree/bindings/timer/arm,sse_timer.yaml new file mode 100644 index 000000000000..37a79f9052d0 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,sse_timer.yaml@@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/arm,sse_timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM SSE(Subsystems for Embedded) system timer + +maintainers: + - Jisheng Zhang <jszhang@kernel.org> + +description: |+ + ARM SSE(Subsystems for Embedded) system timer core may have a system counter + to generate timestamp value, a system timer to raise an interrupt when a + period has elapsed, and a System Watchdog to detect errant system behaviour + then reset the system if a period elapses without ping. + +properties: + compatible: + items: + - enum: + - arm,sse-timer + + reg: + maxItems: 1 + description: The system counter control frame base + + clocks: + maxItems: 1 + + '#address-cells': + enum: [1, 2] + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + '^frame@[0-9a-f]+$': + type: object + additionalProperties: false + description: A timer node has some frame sub-nodes, each frame can be timer frame or watchdog frame. Each frame has the following properties. + properties: + interrupts: + minItems: 1 + items: + - description: timer irq + + reg: + minItems: 1 + items: + - description: 1st view base address + - description: 2nd optional view base address if this is a watchdog frame + + required: + - interrupts + - reg + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + timer@f7f3e000 { + compatible = "arm,sse-timer"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xf7f3e000 0x2000>; + clocks = <&core_clk>; + + frame@f7f20000 { + reg = <0xf7f20000 0x1000>; + interrupts = <0 26 0x8>; + }; + + frame@f7f30000 { + interrupts = <0 15 0x8>; + reg = <0xf7f32000 0x1000>, + <0xf7f33000 0x1000>; + }; + }; + +...-- 2.50.1