[PATCH v18 1/3] dt-bindings: i2c: aspeed,i2c.yaml: add transfer-mode and global-regs properties and update example
From: Ryan Chen <ryan_chen@aspeedtech.com>
Date: 2025-08-20 05:18:44
Also in:
linux-aspeed, linux-devicetree, linux-i2c, lkml, openbmc
Subsystem:
arm/aspeed i2c driver, i2c subsystem host drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
Ryan Chen, Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
The AST2600 I2C controller supports three transfer modes: byte, buffer, and DMA. To allow board designers and firmware to explicitly select the preferred transfer mode for each controller instance. "aspeed,transfer-mode" to allow device tree to specify the desired transfer method used by each I2C controller instance. And AST2600 i2c controller have two register mode, one is legacy register layout which is mix controller/target register control together, another is new mode which is separate controller/target register control. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> --- .../devicetree/bindings/i2c/aspeed,i2c.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
index 5b9bd2feda3b..e021f78b8f8b 100644
--- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml@@ -44,6 +44,34 @@ properties: description: frequency of the bus clock in Hz defaults to 100 kHz when not specified + aspeed,transfer-mode: + description: | + ASPEED ast2600 platform equipped with 16 I2C controllers each i2c controller + have 1 byte transfer buffer(byte mode), 32 bytes buffer(buffer mode), and + share a DMA engine. + Select I2C transfer mode for this controller. Supported values are: + - "byte": Use 1 byte for i2c transmit (1-byte buffer). + - "buffer": Use buffer (32-byte buffer) for i2c transmit. (default) + Better performance then byte mode. + - "dma": Each controller DMA mode is shared DMA engine. The AST2600 SoC + provides a single DMA engine shared for 16 I2C controllers, + so only a limited number of controllers can use DMA simultaneously. + Therefore, the DTS must explicitly assign which controllers are + configured to use DMA. + Only one mode can be selected per controller. + On AST2600, each controller supports all three modes. + If not specified, buffer mode is used by default. + enum: + - byte + - buffer + - dma + + aspeed,global-regs: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of i2c global register node, For control the i2c register + define selection, clock divider mode selection and clock divider control. + required: - reg - compatible
@@ -66,3 +94,14 @@ examples: interrupts = <0>; interrupt-parent = <&i2c_ic>; }; + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + i2c1: i2c@80 { + compatible = "aspeed,ast2600-i2c-bus"; + reg = <0x80 0x80>, <0xc00 0x20>; + aspeed,global-regs = <&i2c_global>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + aspeed,transfer-mode = "buffer"; + };
--
2.34.1