[PATCH 2/7] arm64: dts: allwinner: a523: add third usb2 phy
From: iuncuim <hidden>
Date: 2025-08-16 08:47:44
Also in:
linux-clk, linux-devicetree, linux-phy, linux-sunxi, lkml
Subsystem:
arm/allwinner sunxi soc support, the rest · Maintainers:
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Torvalds
From: Mikhail Kalashnikov <redacted> It seems that there are actually three usb2 phys in the processor, which makes it incompatible with D1. The third phy is used together with USB3/PCIe combophy with DWC3 controller. In the BSP code, the third PHY requires a separate glue driver, but it seems that it is not needed. According to the BSP code, the third phy does not have a reset line; the only reset is declared in the DWC3 node, but none of this is documented. Since sun4i-usb-phy driver requires a reset, I added RST_BUS_3 here. Signed-off-by: Mikhail Kalashnikov <redacted> --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 6b6f2296b..e4ed4fa82 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi@@ -503,22 +503,27 @@ usb_otg: usb@4100000 { }; usbphy: phy@4100400 { - compatible = "allwinner,sun55i-a523-usb-phy", - "allwinner,sun20i-d1-usb-phy"; + compatible = "allwinner,sun55i-a523-usb-phy"; reg = <0x4100400 0x100>, <0x4101800 0x100>, - <0x4200800 0x100>; + <0x4200800 0x100>, + <0x4e00000 0x100>; reg-names = "phy_ctrl", "pmu0", - "pmu1"; + "pmu1", + "pmu2"; clocks = <&osc24M>, - <&osc24M>; + <&osc24M>, + <&ccu CLK_USB2>; clock-names = "usb0_phy", - "usb1_phy"; + "usb1_phy", + "usb2_phy"; resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>; + <&ccu RST_USB_PHY1>, + <&ccu RST_BUS_3>; reset-names = "usb0_reset", - "usb1_reset"; + "usb1_reset", + "usb2_reset"; status = "disabled"; #phy-cells = <1>; };
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2.50.1