Re: [PATCH v4 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control
From: Chen-Yu Tsai <wenst@chromium.org>
Date: 2025-08-15 03:03:52
Also in:
linux-clk, linux-devicetree, linux-mediatek, lkml, netdev
On Tue, Aug 5, 2025 at 10:55 PM Laura Nao [off-list ref] wrote:
On MT8196, there are set/clr registers to control a shared PLL enable register. These are intended to prevent different masters from manipulating the PLLs independently. Add the corresponding en_set_reg and en_clr_reg fields to the mtk_pll_data structure. Reviewed-by: Nícolas F. R. A. Prado <redacted> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <redacted>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>