[PATCH] clk: meson-g12a: fix bit range for fixed sys and hifi pll
From: Da Xue <hidden>
Date: 2025-08-14 20:09:57
Also in:
linux-amlogic, linux-clk, lkml
Subsystem:
arm/amlogic meson soc clock framework, common clk framework, the rest · Maintainers:
Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd, Linus Torvalds
The bit range 17:0 does not match the datasheet for A311D / S905D3. Change the bit range to 19:0 for FIX and HIFI PLLs to match datasheet. There's no frac for sys pll so add that as well. Signed-off-by: Da Xue <redacted> --- drivers/clk/meson/g12a.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 66f0e817e416..f78cca619ca5 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c@@ -157,7 +157,7 @@ static struct clk_regmap g12a_fixed_pll_dco = { .frac = { .reg_off = HHI_FIX_PLL_CNTL1, .shift = 0, - .width = 17, + .width = 19, }, .l = { .reg_off = HHI_FIX_PLL_CNTL0,
@@ -223,6 +223,11 @@ static struct clk_regmap g12a_sys_pll_dco = { .shift = 10, .width = 5, }, + .frac = { + .reg_off = HHI_SYS_PLL_CNTL1, + .shift = 0, + .width = 19, + }, .l = { .reg_off = HHI_SYS_PLL_CNTL0, .shift = 31,
@@ -1901,7 +1906,7 @@ static struct clk_regmap g12a_hifi_pll_dco = { .frac = { .reg_off = HHI_HIFI_PLL_CNTL1, .shift = 0, - .width = 17, + .width = 19, }, .l = { .reg_off = HHI_HIFI_PLL_CNTL0,
--
2.47.2