[PATCH v8 21/21] arm64: dts: apple: t8015: Add CPU PMU nodes
From: Nick Chan <hidden>
Date: 2025-08-11 13:57:00
Also in:
asahi, linux-devicetree, linux-perf-users, lkml
Subsystem:
arm/apple machine support, the rest · Maintainers:
Sven Peter, Janne Grunau, Linus Torvalds
Add CPU PMU nodes for Apple A11 SoC. Signed-off-by: Nick Chan <redacted> --- arch/arm64/boot/dts/apple/t8015.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi
index 12acf8fc8bc6bcde6b11773cadd97e9ee115f510..9bf5157f0e504b7394ef5354411d3d37e8d5760a 100644
--- a/arch/arm64/boot/dts/apple/t8015.dtsi
+++ b/arch/arm64/boot/dts/apple/t8015.dtsi@@ -284,6 +284,18 @@ aic: interrupt-controller@232100000 { #interrupt-cells = <3>; interrupt-controller; power-domains = <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_E>; + cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; + }; + + p-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_P>; + cpus = <&cpu_p0 &cpu_p1>; + }; + }; }; pmgr: power-management@232000000 {
@@ -412,6 +424,18 @@ timer { interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; }; + + pmu-e { + compatible = "apple,mistral-pmu"; + interrupt-parent = <&aic>; + interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu-p { + compatible = "apple,monsoon-pmu"; + interrupt-parent = <&aic>; + interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; + }; }; #include "t8015-pmgr.dtsi"
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2.50.1