[PATCH 15/30] clk: mediatek: Add MT8196 ufssys clock support
From: Laura Nao <hidden>
Date: 2025-06-23 10:30:47
Also in:
linux-clk, linux-devicetree, linux-mediatek, lkml, netdev
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
Add support for the MT8196 ufssys clock controller, which provides clock gate control for UFS. Signed-off-by: Laura Nao <redacted> --- drivers/clk/mediatek/Kconfig | 7 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8196-ufs_ao.c | 84 ++++++++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8196-ufs_ao.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index c55a7c8bdcc5..848624792a23 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig@@ -1068,6 +1068,13 @@ config COMMON_CLK_MT8196 help This driver supports MediaTek MT8196 basic clocks. +config COMMON_CLK_MT8196_UFSSYS + tristate "Clock driver for MediaTek MT8196 ufssys" + depends on COMMON_CLK_MT8196 + default COMMON_CLK_MT8196 + help + This driver supports MediaTek MT8196 ufssys clocks. + config COMMON_CLK_MT8365 tristate "Clock driver for MediaTek MT8365" depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index fc941b5baf04..ee6a1bb5ce38 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile@@ -163,6 +163,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \ clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \ clk-mt8196-peri_ao.o +obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8196-ufs_ao.c b/drivers/clk/mediatek/clk-mt8196-ufs_ao.c
new file mode 100644
index 000000000000..49f4f4af7f41
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8196-ufs_ao.c@@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Guangjie Song <guangjie.song@mediatek.com> + * Copyright (c) 2025 Collabora Ltd. + * Laura Nao <laura.nao@collabora.com> + */ +#include <dt-bindings/clock/mediatek,mt8196-clock.h> +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs ufsao0_cg_regs = { + .set_ofs = 0x108, + .clr_ofs = 0x10c, + .sta_ofs = 0x104, +}; + +static const struct mtk_gate_regs ufsao1_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0xc, + .sta_ofs = 0x4, +}; + +#define GATE_UFSAO0(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &ufsao0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_UFSAO1(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &ufsao1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_OPS_PARENT_ENABLE, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate ufsao_clks[] = { + /* UFSAO0 */ + GATE_UFSAO0(CLK_UFSAO_UFSHCI_UFS, "ufsao_ufshci_ufs", "ufs", 0), + GATE_UFSAO0(CLK_UFSAO_UFSHCI_AES, "ufsao_ufshci_aes", "aes_ufsfde", 1), + /* UFSAO1 */ + GATE_UFSAO1(CLK_UFSAO_UNIPRO_TX_SYM, "ufsao_unipro_tx_sym", "clk26m", 0), + GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM0, "ufsao_unipro_rx_sym0", "clk26m", 1), + GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM1, "ufsao_unipro_rx_sym1", "clk26m", 2), + GATE_UFSAO1(CLK_UFSAO_UNIPRO_SYS, "ufsao_unipro_sys", "ufs", 3), + GATE_UFSAO1(CLK_UFSAO_UNIPRO_SAP, "ufsao_unipro_sap", "clk26m", 4), + GATE_UFSAO1(CLK_UFSAO_PHY_SAP, "ufsao_phy_sap", "clk26m", 8), +}; + +static const struct mtk_clk_desc ufsao_mcd = { + .clks = ufsao_clks, + .num_clks = ARRAY_SIZE(ufsao_clks), +}; + +static const struct of_device_id of_match_clk_mt8196_ufs_ao[] = { + { .compatible = "mediatek,mt8196-ufscfg-ao", .data = &ufsao_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ufs_ao); + +static struct platform_driver clk_mt8196_ufs_ao_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8196-ufs-ao", + .of_match_table = of_match_clk_mt8196_ufs_ao, + }, +}; + +module_platform_driver(clk_mt8196_ufs_ao_drv); +MODULE_DESCRIPTION("MediaTek MT8196 ufs_ao clocks driver"); +MODULE_LICENSE("GPL");
--
2.39.5