Hi Mateusz,

On Wed, 18 Jun 2025 at 18:28, Mateusz Majewski [off-list ref] wrote:

quoted

      /* On exynos5420 the triminfo register is in the shared space */
-     if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
-             trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
-     else
+     if (data->soc == SOC_ARCH_EXYNOS5420 ||
+                     data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
              trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
-
-     sanitize_temp_error(data, trim_info);
+             sanitize_temp_error(data, trim_info);
+     }

If I understand correctly, this means that the triminfo will no longer
be read on other SoCs calling this function (3250, 4412, 5250, 5260). Is
this intended?

Thanks for your feedback.
I will remove the data->soc check for Exynos5420 in the next patch.

By the way, are we sure that data->base_second really is unnecessary?
According to the bindings documentation (in
Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml),
the different address is necessary because the triminfo registers are
misplaced on 5420.

As per my Exynos5422 user manual and DTS mapping
thermal-sensor tmu@10060000 is mapped to CPU0 with tmu_apbif clock
thermal-sensor tmu@10064000 is mapped to CPU1 with tmu_apbif clock
thermal-sensor tmu@10068000 is mapped to CPU2 with tmu_apbif clock
thermal-sensor tmu@1006c000 is mapped to CPU3 with tmu_apbif clock
thermal-sensor tmu@100a0000 is mapped to GPU with tmu_triminfo_apbif clock.

Well, we are using tmu_triminfo_apbif to configure clk_sec, which is
using the data->base to enable the clk.
So, data->base_second is not used any further in the code after we set triminfo

Thank you,
Mateusz Majewski

Thanks
Anand